cache.hh (2811:9da12e9830ce) cache.hh (2812:8e5feae75615)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 124 unchanged lines hidden (view full) ---

133 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
134 blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
135 prefetcher(_prefetcher), prefetchAccess(prefetch_access)
136 {
137 }
138 };
139
140 /** Instantiates a basic cache object. */
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 124 unchanged lines hidden (view full) ---

133 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
134 blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
135 prefetcher(_prefetcher), prefetchAccess(prefetch_access)
136 {
137 }
138 };
139
140 /** Instantiates a basic cache object. */
141 Cache(const std::string &_name, HierParams *hier_params, Params &params);
141 Cache(const std::string &_name, Params ¶ms);
142
143 void regStats();
144
145 /**
146 * Performs the access specified by the request.
147 * @param req The request to perform.
148 * @return The result of the access.
149 */
142
143 void regStats();
144
145 /**
146 * Performs the access specified by the request.
147 * @param req The request to perform.
148 * @return The result of the access.
149 */
150 MemAccessResult access(Packet * &pkt);
150 bool access(Packet * &pkt);
151
152 /**
153 * Selects a request to send on the bus.
154 * @return The memory request to service.
155 */
156 Packet * getPacket();
157
158 /**

--- 69 unchanged lines hidden (view full) ---

228
229 /**
230 * Send a response to the slave interface.
231 * @param req The request being responded to.
232 * @param time The time the response is ready.
233 */
234 void respond(Packet * &pkt, Tick time)
235 {
151
152 /**
153 * Selects a request to send on the bus.
154 * @return The memory request to service.
155 */
156 Packet * getPacket();
157
158 /**

--- 69 unchanged lines hidden (view full) ---

228
229 /**
230 * Send a response to the slave interface.
231 * @param req The request being responded to.
232 * @param time The time the response is ready.
233 */
234 void respond(Packet * &pkt, Tick time)
235 {
236 si->respond(pkt,time);
236 //si->respond(pkt,time);
237 cpuSidePort->sendAtomic(pkt);
237 }
238
239 /**
240 * Perform the access specified in the request and return the estimated
241 * time of completion. This function can either update the hierarchy state
242 * or just perform the access wherever the data is found depending on the
243 * state of the update flag.
244 * @param req The memory request to satisfy

--- 19 unchanged lines hidden --- 		238 }
239
240 /**
241 * Perform the access specified in the request and return the estimated
242 * time of completion. This function can either update the hierarchy state
243 * or just perform the access wherever the data is found depending on the
244 * state of the update flag.
245 * @param req The memory request to satisfy

--- 19 unchanged lines hidden ---