| cache.hh (11452:4bc3a0c0861c) | cache.hh (11484:08b33c52a16d) |
|---|---|
| 1/* 2 * Copyright (c) 2012-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 276 unchanged lines hidden (view full) --- 285 *Handle doing the Compare and Swap function for SPARC. 286 */ 287 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 288 289 /** 290 * Find a block frame for new block at address addr targeting the 291 * given security space, assuming that the block is not currently 292 * in the cache. Append writebacks if any to provided packet | 1/* 2 * Copyright (c) 2012-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 276 unchanged lines hidden (view full) --- 285 *Handle doing the Compare and Swap function for SPARC. 286 */ 287 void cmpAndSwap(CacheBlk *blk, PacketPtr pkt); 288 289 /** 290 * Find a block frame for new block at address addr targeting the 291 * given security space, assuming that the block is not currently 292 * in the cache. Append writebacks if any to provided packet |
| 293 * list. Return free block frame. May return NULL if there are | 293 * list. Return free block frame. May return nullptr if there are |
| 294 * no replaceable blocks at the moment. 295 */ 296 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 297 298 /** 299 * Invalidate a cache block. 300 * 301 * @param blk Block to invalidate --- 157 unchanged lines hidden (view full) --- 459 */ 460 bool invalidateVisitor(CacheBlk &blk); 461 462 /** 463 * Create an appropriate downstream bus request packet for the 464 * given parameters. 465 * @param cpu_pkt The miss that needs to be satisfied. 466 * @param blk The block currently in the cache corresponding to | 294 * no replaceable blocks at the moment. 295 */ 296 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks); 297 298 /** 299 * Invalidate a cache block. 300 * 301 * @param blk Block to invalidate --- 157 unchanged lines hidden (view full) --- 459 */ 460 bool invalidateVisitor(CacheBlk &blk); 461 462 /** 463 * Create an appropriate downstream bus request packet for the 464 * given parameters. 465 * @param cpu_pkt The miss that needs to be satisfied. 466 * @param blk The block currently in the cache corresponding to |
| 467 * cpu_pkt (NULL if none). | 467 * cpu_pkt (nullptr if none). |
| 468 * @param needsWritable Indicates that the block must be writable 469 * even if the request in cpu_pkt doesn't indicate that. | 468 * @param needsWritable Indicates that the block must be writable 469 * even if the request in cpu_pkt doesn't indicate that. |
| 470 * @return A new Packet containing the request, or NULL if the | 470 * @return A new Packet containing the request, or nullptr if the |
| 471 * current request in cpu_pkt should just be forwarded on. 472 */ 473 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 474 bool needsWritable) const; 475 476 /** 477 * Return the next queue entry to service, either a pending miss 478 * from the MSHR queue, a buffered write from the write buffer, or --- 131 unchanged lines hidden --- | 471 * current request in cpu_pkt should just be forwarded on. 472 */ 473 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 474 bool needsWritable) const; 475 476 /** 477 * Return the next queue entry to service, either a pending miss 478 * from the MSHR queue, a buffered write from the write buffer, or --- 131 unchanged lines hidden --- |