cache.hh (11211:4e70e13c1a2c) cache.hh (11276:3561d002d8c7)
1/*
2 * Copyright (c) 2012-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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242 * An event to writeback the tempBlock after recvAtomic
243 * finishes. To avoid other calls to recvAtomic getting in
244 * between, we create this event with a higher priority.
245 */
246 EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
247 writebackTempBlockAtomicEvent;
248
249 /**
1/*
2 * Copyright (c) 2012-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 233 unchanged lines hidden (view full) ---

242 * An event to writeback the tempBlock after recvAtomic
243 * finishes. To avoid other calls to recvAtomic getting in
244 * between, we create this event with a higher priority.
245 */
246 EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
247 writebackTempBlockAtomicEvent;
248
249 /**
250 * Store the outstanding requests that we are expecting snoop
251 * responses from so we can determine which snoop responses we
252 * generated and which ones were merely forwarded.
253 */
254 std::unordered_set<RequestPtr> outstandingSnoop;
255
256 /**
250 * Does all the processing necessary to perform the provided request.
251 * @param pkt The memory request to perform.
252 * @param blk The cache block to be updated.
253 * @param lat The latency of the access.
254 * @param writebacks List for any writebacks that need to be performed.
255 * @return Boolean indicating whether the request was satisfied.
256 */
257 bool access(PacketPtr pkt, CacheBlk *&blk,

--- 318 unchanged lines hidden --- 		257 * Does all the processing necessary to perform the provided request.
258 * @param pkt The memory request to perform.
259 * @param blk The cache block to be updated.
260 * @param lat The latency of the access.
261 * @param writebacks List for any writebacks that need to be performed.
262 * @return Boolean indicating whether the request was satisfied.
263 */
264 bool access(PacketPtr pkt, CacheBlk *&blk,

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