cache.hh (11190:0964165d1857) cache.hh (11197:f8fdd931e674)
1/*
1/*
2 * Copyright (c) 2012-2014 ARM Limited
2 * Copyright (c) 2012-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __MEM_CACHE_CACHE_HH__
53#define __MEM_CACHE_CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __MEM_CACHE_CACHE_HH__
53#define __MEM_CACHE_CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "enums/Clusivity.hh"
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "mem/cache/tags/base.hh"
60#include "params/Cache.hh"
61#include "sim/eventq.hh"
62
63//Forward decleration

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189 */
190 void promoteWholeLineWrites(PacketPtr pkt);
191
192 /**
193 * Notify the prefetcher on every access, not just misses.
194 */
195 const bool prefetchOnAccess;
196
57#include "mem/cache/base.hh"
58#include "mem/cache/blk.hh"
59#include "mem/cache/mshr.hh"
60#include "mem/cache/tags/base.hh"
61#include "params/Cache.hh"
62#include "sim/eventq.hh"
63
64//Forward decleration

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190 */
191 void promoteWholeLineWrites(PacketPtr pkt);
192
193 /**
194 * Notify the prefetcher on every access, not just misses.
195 */
196 const bool prefetchOnAccess;
197
198 /**
199 * Clusivity with respect to the upstream cache, determining if we
200 * fill into both this cache and the cache above on a miss. Note
201 * that we currently do not support strict clusivity policies.
202 */
203 const Enums::Clusivity clusivity;
204
197 /**
198 * Upstream caches need this packet until true is returned, so
199 * hold it for deletion until a subsequent call
200 */
201 std::unique_ptr<Packet> pendingDelete;
202
203 /**
205 /**
206 * Upstream caches need this packet until true is returned, so
207 * hold it for deletion until a subsequent call
208 */
209 std::unique_ptr<Packet> pendingDelete;
210
211 /**
212 * Writebacks from the tempBlock, resulting on the response path
213 * in atomic mode, must happen after the call to recvAtomic has
214 * finished (for the right ordering of the packets). We therefore
215 * need to hold on to the packets, and have a method and an event
216 * to send them.
217 */
218 PacketPtr tempBlockWriteback;
219
220 /**
221 * Send the outstanding tempBlock writeback. To be called after
222 * recvAtomic finishes in cases where the block we filled is in
223 * fact the tempBlock, and now needs to be written back.
224 */
225 void writebackTempBlockAtomic() {
226 assert(tempBlockWriteback != nullptr);
227 PacketList writebacks{tempBlockWriteback};
228 doWritebacksAtomic(writebacks);
229 tempBlockWriteback = nullptr;
230 }
231
232 /**
233 * An event to writeback the tempBlock after recvAtomic
234 * finishes. To avoid other calls to recvAtomic getting in
235 * between, we create this event with a higher priority.
236 */
237 EventWrapper<Cache, &Cache::writebackTempBlockAtomic> \
238 writebackTempBlockAtomicEvent;
239
240 /**
204 * Does all the processing necessary to perform the provided request.
205 * @param pkt The memory request to perform.
206 * @param blk The cache block to be updated.
207 * @param lat The latency of the access.
208 * @param writebacks List for any writebacks that need to be performed.
209 * @return Boolean indicating whether the request was satisfied.
210 */
211 bool access(PacketPtr pkt, CacheBlk *&blk,

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221 * given security space, assuming that the block is not currently
222 * in the cache. Append writebacks if any to provided packet
223 * list. Return free block frame. May return NULL if there are
224 * no replaceable blocks at the moment.
225 */
226 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
227
228 /**
241 * Does all the processing necessary to perform the provided request.
242 * @param pkt The memory request to perform.
243 * @param blk The cache block to be updated.
244 * @param lat The latency of the access.
245 * @param writebacks List for any writebacks that need to be performed.
246 * @return Boolean indicating whether the request was satisfied.
247 */
248 bool access(PacketPtr pkt, CacheBlk *&blk,

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258 * given security space, assuming that the block is not currently
259 * in the cache. Append writebacks if any to provided packet
260 * list. Return free block frame. May return NULL if there are
261 * no replaceable blocks at the moment.
262 */
263 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
264
265 /**
266 * Invalidate a cache block.
267 *
268 * @param blk Block to invalidate
269 */
270 void invalidateBlock(CacheBlk *blk);
271
272 /**
229 * Populates a cache block and handles all outstanding requests for the
230 * satisfied fill request. This version takes two memory requests. One
231 * contains the fill data, the other is an optional target to satisfy.
232 * @param pkt The memory request with the fill data.
233 * @param blk The cache block if it already exists.
234 * @param writebacks List for any writebacks that need to be performed.
273 * Populates a cache block and handles all outstanding requests for the
274 * satisfied fill request. This version takes two memory requests. One
275 * contains the fill data, the other is an optional target to satisfy.
276 * @param pkt The memory request with the fill data.
277 * @param blk The cache block if it already exists.
278 * @param writebacks List for any writebacks that need to be performed.
279 * @param allocate Whether to allocate a block or use the temp block
235 * @return Pointer to the new cache block.
236 */
237 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
280 * @return Pointer to the new cache block.
281 */
282 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
238 PacketList &writebacks);
283 PacketList &writebacks, bool allocate);
239
284
285 /**
286 * Determine whether we should allocate on a fill or not. If this
287 * cache is mostly inclusive with regards to the upstream cache(s)
288 * we always allocate (for any non-forwarded and cacheable
289 * requests). In the case of a mostly exclusive cache, we allocate
290 * on fill if the packet did not come from a cache, thus if we:
291 * are dealing with a whole-line write (the latter behaves much
292 * like a writeback), the original target packet came from a
293 * non-caching source, or if we are performing a prefetch or LLSC.
294 *
295 * @param cmd Command of the incoming requesting packet
296 * @return Whether we should allocate on the fill
297 */
298 inline bool allocOnFill(MemCmd cmd) const
299 {
300 return clusivity == Enums::mostly_incl ||
301 cmd == MemCmd::WriteLineReq ||
302 cmd == MemCmd::ReadReq ||
303 cmd == MemCmd::WriteReq ||
304 cmd.isPrefetch() ||
305 cmd.isLLSC();
306 }
240
241 /**
242 * Performs the access specified by the request.
243 * @param pkt The request to perform.
244 * @return The result of the access.
245 */
246 bool recvTimingReq(PacketPtr pkt);
247

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308 /**
309 * Performs the access specified by the request.
310 * @param pkt The request to perform.
311 * @return The result of the access.
312 */
313 bool recvTimingReq(PacketPtr pkt);
314

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