1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 123 unchanged lines hidden (view full) --- 132 133 /** Coherence protocol. */ 134 Coherence *coherence; 135 136 /** Prefetcher */ 137 BasePrefetcher *prefetcher; 138 139 /** |
140 * Can this cache should allocate a block on a line-sized write miss. 141 */ 142 const bool doFastWrites; 143 144 const bool prefetchMiss; 145 146 /** 147 * Handle a replacement for the given request. --- 134 unchanged lines hidden (view full) --- 282 /** 283 * Squash all requests associated with specified thread. 284 * intended for use by I-cache. 285 * @param threadNum The thread to squash. 286 */ 287 void squash(int threadNum); 288 289 /** |
290 * Selects a outstanding request to service. 291 * @return The request to service, NULL if none found. 292 */ 293 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk, 294 bool needsExclusive); 295 MSHR *getNextMSHR(); 296 PacketPtr getTimingPacket(); 297 --- 36 unchanged lines hidden --- |