1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Erik Hallnor 29 * Dave Greene 30 * Steve Reinhardt |
31 * Ron Dreslinski |
32 */ 33 34/** 35 * @file 36 * Describes a cache based on template policies. 37 */ 38 39#ifndef __CACHE_HH__ 40#define __CACHE_HH__ 41 42#include "base/compression/base.hh" 43#include "base/misc.hh" // fatal, panic, and warn 44#include "cpu/smt.hh" // SMT_MAX_THREADS 45 46#include "mem/cache/base_cache.hh" 47#include "mem/cache/cache_blk.hh" 48#include "mem/cache/miss/miss_buffer.hh" 49 |
50#include "sim/eventq.hh" 51 |
52//Forward decleration 53class MSHR; 54class BasePrefetcher; 55 56/** 57 * A template-policy based cache. The behavior of the cache can be altered by 58 * supplying different template policies. TagStore handles all tag and data 59 * storage @sa TagStore. Buffering handles all misses and writes/writebacks --- 21 unchanged lines hidden (view full) --- 81 82 // BaseCache::CachePort just has a BaseCache *; this function 83 // lets us get back the type info we lost when we stored the 84 // cache pointer there. 85 Cache<TagStore,Coherence> *myCache() { 86 return static_cast<Cache<TagStore,Coherence> *>(cache); 87 } 88 |
89 void processRequestEvent(); 90 void processResponseEvent(); 91 |
92 virtual bool recvTiming(PacketPtr pkt); 93 |
94 virtual void recvRetry(); 95 |
96 virtual Tick recvAtomic(PacketPtr pkt); 97 98 virtual void recvFunctional(PacketPtr pkt); |
99 100 typedef EventWrapper<CpuSidePort, &CpuSidePort::processResponseEvent> 101 ResponseEvent; 102 103 typedef EventWrapper<CpuSidePort, &CpuSidePort::processRequestEvent> 104 RequestEvent; 105 106 virtual void scheduleRequestEvent(Tick t) { 107 new RequestEvent(this, t); 108 } |
109 }; 110 111 class MemSidePort : public CachePort 112 { 113 public: 114 MemSidePort(const std::string &_name, 115 Cache<TagStore,Coherence> *_cache); 116 117 // BaseCache::CachePort just has a BaseCache *; this function 118 // lets us get back the type info we lost when we stored the 119 // cache pointer there. 120 Cache<TagStore,Coherence> *myCache() { 121 return static_cast<Cache<TagStore,Coherence> *>(cache); 122 } 123 |
124 void processRequestEvent(); 125 void processResponseEvent(); 126 |
127 virtual bool recvTiming(PacketPtr pkt); 128 |
129 virtual void recvRetry(); 130 |
131 virtual Tick recvAtomic(PacketPtr pkt); 132 133 virtual void recvFunctional(PacketPtr pkt); |
134 135 typedef EventWrapper<MemSidePort, &MemSidePort::processResponseEvent> 136 ResponseEvent; 137 138 typedef EventWrapper<MemSidePort, &MemSidePort::processRequestEvent> 139 RequestEvent; 140 141 virtual void scheduleRequestEvent(Tick t) { 142 new RequestEvent(this, t); 143 } |
144 }; 145 146 /** Tag and data Storage */ 147 TagStore *tags; 148 /** Miss and Writeback handler */ 149 MissBuffer *missQueue; 150 /** Coherence protocol. */ 151 Coherence *coherence; --- 215 unchanged lines hidden (view full) --- 367 }; 368 369 /** Instantiates a basic cache object. */ 370 Cache(const std::string &_name, Params ¶ms); 371 372 virtual Port *getPort(const std::string &if_name, int idx = -1); 373 virtual void deletePortRefs(Port *p); 374 |
375 void regStats(); 376 377 /** 378 * Performs the access specified by the request. 379 * @param pkt The request to perform. 380 * @return The result of the access. 381 */ 382 bool access(PacketPtr &pkt); 383 384 /** 385 * Selects a request to send on the bus. 386 * @return The memory request to service. 387 */ |
388 PacketPtr getPacket(); |
389 390 /** 391 * Was the request was sent successfully? 392 * @param pkt The request. 393 * @param success True if the request was sent successfully. 394 */ |
395 void sendResult(PacketPtr &pkt, MSHR* mshr, bool success); |
396 397 /** |
398 * Handles a response (cache line fill/write ack) from the bus. 399 * @param pkt The request being responded to. 400 */ 401 void handleResponse(PacketPtr &pkt); 402 403 /** |
404 * Snoops bus transactions to maintain coherence. 405 * @param pkt The current bus transaction. 406 */ 407 void snoop(PacketPtr &pkt); 408 409 void snoopResponse(PacketPtr &pkt); 410 411 /** --- 53 unchanged lines hidden --- |