1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 61 unchanged lines hidden (view full) --- 70 /** Miss and Writeback handler */ 71 Buffering *missQueue; 72 /** Coherence protocol. */ 73 Coherence *coherence; 74 75 /** Prefetcher */ 76 Prefetcher<TagStore, Buffering> *prefetcher; 77 |
78 /** 79 * The clock ratio of the outgoing bus. 80 * Used for calculating critical word first. 81 */ 82 int busRatio; 83 84 /** 85 * The bus width in bytes of the outgoing bus. --- 8 unchanged lines hidden (view full) --- 94 95 /** 96 * A permanent mem req to always be used to cause invalidations. 97 * Used to append to target list, to cause an invalidation. 98 */ 99 Packet * invalidatePkt; 100 Request *invalidateReq; 101 |
102 public: 103 104 class Params 105 { 106 public: 107 TagStore *tags; 108 Buffering *missQueue; 109 Coherence *coherence; |
110 BaseCache::Params baseParams; 111 Prefetcher<TagStore, Buffering> *prefetcher; 112 bool prefetchAccess; 113 int hitLatency; 114 115 Params(TagStore *_tags, Buffering *mq, Coherence *coh, |
116 BaseCache::Params params, |
117 Prefetcher<TagStore, Buffering> *_prefetcher, 118 bool prefetch_access, int hit_latency) |
119 : tags(_tags), missQueue(mq), coherence(coh), 120 baseParams(params), |
121 prefetcher(_prefetcher), prefetchAccess(prefetch_access), 122 hitLatency(hit_latency) 123 { 124 } 125 }; 126 127 /** Instantiates a basic cache object. */ 128 Cache(const std::string &_name, Params ¶ms); --- 38 unchanged lines hidden (view full) --- 167 168 /** 169 * Handles a response (cache line fill/write ack) from the bus. 170 * @param pkt The request being responded to. 171 */ 172 void handleResponse(Packet * &pkt); 173 174 /** |
175 * Selects a coherence message to forward to lower levels of the hierarchy. 176 * @return The coherence message to forward. 177 */ 178 virtual Packet * getCoherencePacket(); 179 180 /** 181 * Snoops bus transactions to maintain coherence. 182 * @param pkt The current bus transaction. --- 59 unchanged lines hidden --- |