1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 132 unchanged lines hidden (view full) --- 141 hitLatency(hit_latency) 142 { 143 } 144 }; 145 146 /** Instantiates a basic cache object. */ 147 Cache(const std::string &_name, Params ¶ms); 148 |
149 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort, |
150 bool isCpuSide); 151 |
152 virtual Tick doAtomicAccess(Packet *pkt, CachePort *cachePort, |
153 bool isCpuSide); 154 |
155 virtual void doFunctionalAccess(Packet *pkt, CachePort *cachePort, |
156 bool isCpuSide); 157 |
158 virtual void recvStatusChange(Port::Status status, bool isCpuSide); |
159 160 void regStats(); 161 162 /** 163 * Performs the access specified by the request. 164 * @param req The request to perform. 165 * @return The result of the access. 166 */ --- 115 unchanged lines hidden --- |