1/* |
2 * Copyright (c) 2012-2016 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 121 unchanged lines hidden (view full) --- 132 133 /** 134 * Override the normal sendDeferredPacket and do not only 135 * consider the transmit list (used for responses), but also 136 * requests. 137 */ 138 virtual void sendDeferredPacket(); 139 |
140 /** 141 * Check if there is a conflicting snoop response about to be 142 * send out, and if so simply stall any requests, and schedule 143 * a send event at the same time as the next snoop response is 144 * being sent out. 145 */ 146 bool checkConflictingSnoop(Addr addr) 147 { 148 if (snoopRespQueue.hasAddr(addr)) { 149 DPRINTF(CachePort, "Waiting for snoop response to be " 150 "sent\n"); 151 Tick when = snoopRespQueue.deferredPacketReadyTime(); 152 schedSendEvent(when); 153 return true; 154 } 155 return false; 156 } |
157 }; 158 159 /** 160 * The memory-side port extends the base cache master port with 161 * access functions for functional, atomic and timing snoops. 162 */ 163 class MemSidePort : public CacheMasterPort 164 { --- 186 unchanged lines hidden (view full) --- 351 void doWritebacks(PacketList& writebacks, Tick forward_time); 352 353 /** 354 * Send writebacks down the memory hierarchy in atomic mode 355 */ 356 void doWritebacksAtomic(PacketList& writebacks); 357 358 /** |
359 * Handling the special case of uncacheable write responses to 360 * make recvTimingResp less cluttered. 361 */ 362 void handleUncacheableWriteResp(PacketPtr pkt); 363 364 /** |
365 * Handles a response (cache line fill/write ack) from the bus. 366 * @param pkt The response packet 367 */ 368 void recvTimingResp(PacketPtr pkt); 369 370 /** 371 * Snoops bus transactions to maintain coherence. 372 * @param pkt The current bus transaction. --- 96 unchanged lines hidden (view full) --- 469 * even if the request in cpu_pkt doesn't indicate that. 470 * @return A new Packet containing the request, or NULL if the 471 * current request in cpu_pkt should just be forwarded on. 472 */ 473 PacketPtr getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 474 bool needsExclusive) const; 475 476 /** |
477 * Return the next queue entry to service, either a pending miss 478 * from the MSHR queue, a buffered write from the write buffer, or 479 * something from the prefetcher. This function is responsible 480 * for prioritizing among those sources on the fly. |
481 */ |
482 QueueEntry* getNextQueueEntry(); |
483 484 /** 485 * Send up a snoop request and find cached copies. If cached copies are 486 * found, set the BLOCK_CACHED flag in pkt. 487 */ 488 bool isCachedAbove(PacketPtr pkt, bool is_timing = true) const; 489 490 /** |
491 * Return whether there are any outstanding misses. 492 */ 493 bool outstandingMisses() const 494 { |
495 return !mshrQueue.isEmpty(); |
496 } 497 498 CacheBlk *findBlock(Addr addr, bool is_secure) const { 499 return tags->findBlock(addr, is_secure); 500 } 501 502 bool inCache(Addr addr, bool is_secure) const override { 503 return (tags->findBlock(addr, is_secure) != 0); 504 } 505 506 bool inMissQueue(Addr addr, bool is_secure) const override { 507 return (mshrQueue.findMatch(addr, is_secure) != 0); 508 } 509 510 /** 511 * Find next request ready time from among possible sources. 512 */ |
513 Tick nextQueueReadyTime() const; |
514 515 public: 516 /** Instantiates a basic cache object. */ 517 Cache(const CacheParams *p); 518 519 /** Non-default destructor is needed to deallocate memory. */ 520 virtual ~Cache(); 521 522 void regStats() override; 523 |
524 /** 525 * Take an MSHR, turn it into a suitable downstream packet, and 526 * send it out. This construct allows a queue entry to choose a suitable 527 * approach based on its type. 528 * 529 * @param mshr The MSHR to turn into a packet and send 530 * @return True if the port is waiting for a retry 531 */ 532 bool sendMSHRQueuePacket(MSHR* mshr); 533 534 /** 535 * Similar to sendMSHR, but for a write-queue entry 536 * instead. Create the packet, and send it, and if successful also 537 * mark the entry in service. 538 * 539 * @param wq_entry The write-queue entry to turn into a packet and send 540 * @return True if the port is waiting for a retry 541 */ 542 bool sendWriteQueuePacket(WriteQueueEntry* wq_entry); 543 |
544 /** serialize the state of the caches 545 * We currently don't support checkpointing cache state, so this panics. 546 */ 547 void serialize(CheckpointOut &cp) const override; 548 void unserialize(CheckpointIn &cp) override; 549}; 550 551/** --- 58 unchanged lines hidden --- |