1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Dave Greene
42 * Steve Reinhardt
43 * Ron Dreslinski
44 * Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __CACHE_HH__
53#define __CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "sim/eventq.hh"
60
61//Forward decleration
62class BasePrefetcher;
63
64/**
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore.
68 */
69template <class TagStore>
70class Cache : public BaseCache
71{
72 public:
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
77
78 protected:
79
80 /**
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
83 */
84 class CpuSidePort : public CacheSlavePort
85 {
86 private:
87
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
90
91 protected:
92
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Dave Greene
42 * Steve Reinhardt
43 * Ron Dreslinski
44 * Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __CACHE_HH__
53#define __CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "sim/eventq.hh"
60
61//Forward decleration
62class BasePrefetcher;
63
64/**
65 * A template-policy based cache. The behavior of the cache can be altered by
66 * supplying different template policies. TagStore handles all tag and data
67 * storage @sa TagStore.
68 */
69template <class TagStore>
70class Cache : public BaseCache
71{
72 public:
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
77
78 protected:
79
80 /**
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
83 */
84 class CpuSidePort : public CacheSlavePort
85 {
86 private:
87
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
90
91 protected:
92
|
| 93 virtual bool recvTimingSnoop(PacketPtr pkt);
94
|
93 virtual bool recvTiming(PacketPtr pkt);
94
95 virtual Tick recvAtomic(PacketPtr pkt);
96
97 virtual void recvFunctional(PacketPtr pkt);
98
99 virtual unsigned deviceBlockSize() const
100 { return cache->getBlockSize(); }
101
102 virtual AddrRangeList getAddrRanges();
103
104 public:
105
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
108
109 };
110
111 /**
112 * Override the default behaviour of sendDeferredPacket to enable
113 * the memory-side cache port to also send requests based on the
114 * current MSHR status. This queue has a pointer to our specific
115 * cache implementation and is used by the MemSidePort.
116 */
117 class MemSidePacketQueue : public PacketQueue
118 {
119
120 protected:
121
122 Cache<TagStore> &cache;
123
124 public:
125
126 MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
127 const std::string &label) :
128 PacketQueue(cache, port, label), cache(cache) { }
129
130 /**
131 * Override the normal sendDeferredPacket and do not only
132 * consider the transmit list (used for responses), but also
133 * requests.
134 */
135 virtual void sendDeferredPacket();
136
137 };
138
139 /**
140 * The memory-side port extends the base cache master port with
141 * access functions for functional, atomic and timing snoops.
142 */
143 class MemSidePort : public CacheMasterPort
144 {
145 private:
146
147 /** The cache-specific queue. */
148 MemSidePacketQueue _queue;
149
150 // a pointer to our specific cache implementation
151 Cache<TagStore> *cache;
152
153 protected:
154
| 95 virtual bool recvTiming(PacketPtr pkt);
96
97 virtual Tick recvAtomic(PacketPtr pkt);
98
99 virtual void recvFunctional(PacketPtr pkt);
100
101 virtual unsigned deviceBlockSize() const
102 { return cache->getBlockSize(); }
103
104 virtual AddrRangeList getAddrRanges();
105
106 public:
107
108 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
109 const std::string &_label);
110
111 };
112
113 /**
114 * Override the default behaviour of sendDeferredPacket to enable
115 * the memory-side cache port to also send requests based on the
116 * current MSHR status. This queue has a pointer to our specific
117 * cache implementation and is used by the MemSidePort.
118 */
119 class MemSidePacketQueue : public PacketQueue
120 {
121
122 protected:
123
124 Cache<TagStore> &cache;
125
126 public:
127
128 MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
129 const std::string &label) :
130 PacketQueue(cache, port, label), cache(cache) { }
131
132 /**
133 * Override the normal sendDeferredPacket and do not only
134 * consider the transmit list (used for responses), but also
135 * requests.
136 */
137 virtual void sendDeferredPacket();
138
139 };
140
141 /**
142 * The memory-side port extends the base cache master port with
143 * access functions for functional, atomic and timing snoops.
144 */
145 class MemSidePort : public CacheMasterPort
146 {
147 private:
148
149 /** The cache-specific queue. */
150 MemSidePacketQueue _queue;
151
152 // a pointer to our specific cache implementation
153 Cache<TagStore> *cache;
154
155 protected:
156
|
| 157 virtual bool recvTimingSnoop(PacketPtr pkt);
158
|
155 virtual bool recvTiming(PacketPtr pkt);
156
| 159 virtual bool recvTiming(PacketPtr pkt);
160
|
157 virtual Tick recvAtomic(PacketPtr pkt);
| 161 virtual Tick recvAtomicSnoop(PacketPtr pkt);
|
158
| 162
|
159 virtual void recvFunctional(PacketPtr pkt);
| 163 virtual void recvFunctionalSnoop(PacketPtr pkt);
|
160
161 virtual unsigned deviceBlockSize() const
162 { return cache->getBlockSize(); }
163
164 public:
165
166 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
167 const std::string &_label);
168 };
169
170 /** Tag and data Storage */
171 TagStore *tags;
172
173 /** Prefetcher */
174 BasePrefetcher *prefetcher;
175
176 /** Temporary cache block for occasional transitory use */
177 BlkType *tempBlock;
178
179 /**
180 * This cache should allocate a block on a line-sized write miss.
181 */
182 const bool doFastWrites;
183
184 /**
185 * Notify the prefetcher on every access, not just misses.
186 */
187 const bool prefetchOnAccess;
188
189 /**
190 * Does all the processing necessary to perform the provided request.
191 * @param pkt The memory request to perform.
192 * @param lat The latency of the access.
193 * @param writebacks List for any writebacks that need to be performed.
194 * @param update True if the replacement data should be updated.
195 * @return Boolean indicating whether the request was satisfied.
196 */
197 bool access(PacketPtr pkt, BlkType *&blk,
198 int &lat, PacketList &writebacks);
199
200 /**
201 *Handle doing the Compare and Swap function for SPARC.
202 */
203 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
204
205 /**
206 * Find a block frame for new block at address addr, assuming that
207 * the block is not currently in the cache. Append writebacks if
208 * any to provided packet list. Return free block frame. May
209 * return NULL if there are no replaceable blocks at the moment.
210 */
211 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
212
213 /**
214 * Populates a cache block and handles all outstanding requests for the
215 * satisfied fill request. This version takes two memory requests. One
216 * contains the fill data, the other is an optional target to satisfy.
217 * @param pkt The memory request with the fill data.
218 * @param blk The cache block if it already exists.
219 * @param writebacks List for any writebacks that need to be performed.
220 * @return Pointer to the new cache block.
221 */
222 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
223 PacketList &writebacks);
224
225 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
226 bool deferred_response = false,
227 bool pending_downgrade = false);
228 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
229
230 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
231 bool already_copied, bool pending_inval);
232
233 /**
234 * Sets the blk to the new state.
235 * @param blk The cache block being snooped.
236 * @param new_state The new coherence state for the block.
237 */
238 void handleSnoop(PacketPtr ptk, BlkType *blk,
239 bool is_timing, bool is_deferred, bool pending_inval);
240
241 /**
242 * Create a writeback request for the given block.
243 * @param blk The block to writeback.
244 * @return The writeback request for the block.
245 */
246 PacketPtr writebackBlk(BlkType *blk);
247
248 public:
249 /** Instantiates a basic cache object. */
250 Cache(const Params *p, TagStore *tags);
251
252 void regStats();
253
254 /**
255 * Performs the access specified by the request.
256 * @param pkt The request to perform.
257 * @return The result of the access.
258 */
259 bool timingAccess(PacketPtr pkt);
260
261 /**
262 * Performs the access specified by the request.
263 * @param pkt The request to perform.
264 * @return The result of the access.
265 */
266 Tick atomicAccess(PacketPtr pkt);
267
268 /**
269 * Performs the access specified by the request.
270 * @param pkt The request to perform.
271 * @param fromCpuSide from the CPU side port or the memory side port
272 */
273 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
274
275 /**
276 * Handles a response (cache line fill/write ack) from the bus.
277 * @param pkt The request being responded to.
278 */
279 void handleResponse(PacketPtr pkt);
280
281 /**
282 * Snoops bus transactions to maintain coherence.
283 * @param pkt The current bus transaction.
284 */
285 void snoopTiming(PacketPtr pkt);
286
287 /**
288 * Snoop for the provided request in the cache and return the estimated
289 * time of completion.
290 * @param pkt The memory request to snoop
291 * @return The estimated completion time.
292 */
293 Tick snoopAtomic(PacketPtr pkt);
294
295 /**
296 * Squash all requests associated with specified thread.
297 * intended for use by I-cache.
298 * @param threadNum The thread to squash.
299 */
300 void squash(int threadNum);
301
302 /**
303 * Generate an appropriate downstream bus request packet for the
304 * given parameters.
305 * @param cpu_pkt The upstream request that needs to be satisfied.
306 * @param blk The block currently in the cache corresponding to
307 * cpu_pkt (NULL if none).
308 * @param needsExclusive Indicates that an exclusive copy is required
309 * even if the request in cpu_pkt doesn't indicate that.
310 * @return A new Packet containing the request, or NULL if the
311 * current request in cpu_pkt should just be forwarded on.
312 */
313 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
314 bool needsExclusive);
315
316 /**
317 * Return the next MSHR to service, either a pending miss from the
318 * mshrQueue, a buffered write from the write buffer, or something
319 * from the prefetcher. This function is responsible for
320 * prioritizing among those sources on the fly.
321 */
322 MSHR *getNextMSHR();
323
324 /**
325 * Selects an outstanding request to service. Called when the
326 * cache gets granted the downstream bus in timing mode.
327 * @return The request to service, NULL if none found.
328 */
329 PacketPtr getTimingPacket();
330
331 /**
332 * Marks a request as in service (sent on the bus). This can have side
333 * effect since storage for no response commands is deallocated once they
334 * are successfully sent.
335 * @param pkt The request that was sent on the bus.
336 */
337 void markInService(MSHR *mshr, PacketPtr pkt = 0);
338
339 /**
340 * Perform the given writeback request.
341 * @param pkt The writeback request.
342 */
343 void doWriteback(PacketPtr pkt);
344
345 /**
346 * Return whether there are any outstanding misses.
347 */
348 bool outstandingMisses() const
349 {
350 return mshrQueue.allocated != 0;
351 }
352
353 CacheBlk *findBlock(Addr addr) {
354 return tags->findBlock(addr);
355 }
356
357 bool inCache(Addr addr) {
358 return (tags->findBlock(addr) != 0);
359 }
360
361 bool inMissQueue(Addr addr) {
362 return (mshrQueue.findMatch(addr) != 0);
363 }
364
365 /**
366 * Find next request ready time from among possible sources.
367 */
368 Tick nextMSHRReadyTime();
369};
370
371#endif // __CACHE_HH__
| 164
165 virtual unsigned deviceBlockSize() const
166 { return cache->getBlockSize(); }
167
168 public:
169
170 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
171 const std::string &_label);
172 };
173
174 /** Tag and data Storage */
175 TagStore *tags;
176
177 /** Prefetcher */
178 BasePrefetcher *prefetcher;
179
180 /** Temporary cache block for occasional transitory use */
181 BlkType *tempBlock;
182
183 /**
184 * This cache should allocate a block on a line-sized write miss.
185 */
186 const bool doFastWrites;
187
188 /**
189 * Notify the prefetcher on every access, not just misses.
190 */
191 const bool prefetchOnAccess;
192
193 /**
194 * Does all the processing necessary to perform the provided request.
195 * @param pkt The memory request to perform.
196 * @param lat The latency of the access.
197 * @param writebacks List for any writebacks that need to be performed.
198 * @param update True if the replacement data should be updated.
199 * @return Boolean indicating whether the request was satisfied.
200 */
201 bool access(PacketPtr pkt, BlkType *&blk,
202 int &lat, PacketList &writebacks);
203
204 /**
205 *Handle doing the Compare and Swap function for SPARC.
206 */
207 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
208
209 /**
210 * Find a block frame for new block at address addr, assuming that
211 * the block is not currently in the cache. Append writebacks if
212 * any to provided packet list. Return free block frame. May
213 * return NULL if there are no replaceable blocks at the moment.
214 */
215 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
216
217 /**
218 * Populates a cache block and handles all outstanding requests for the
219 * satisfied fill request. This version takes two memory requests. One
220 * contains the fill data, the other is an optional target to satisfy.
221 * @param pkt The memory request with the fill data.
222 * @param blk The cache block if it already exists.
223 * @param writebacks List for any writebacks that need to be performed.
224 * @return Pointer to the new cache block.
225 */
226 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
227 PacketList &writebacks);
228
229 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk,
230 bool deferred_response = false,
231 bool pending_downgrade = false);
232 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
233
234 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
235 bool already_copied, bool pending_inval);
236
237 /**
238 * Sets the blk to the new state.
239 * @param blk The cache block being snooped.
240 * @param new_state The new coherence state for the block.
241 */
242 void handleSnoop(PacketPtr ptk, BlkType *blk,
243 bool is_timing, bool is_deferred, bool pending_inval);
244
245 /**
246 * Create a writeback request for the given block.
247 * @param blk The block to writeback.
248 * @return The writeback request for the block.
249 */
250 PacketPtr writebackBlk(BlkType *blk);
251
252 public:
253 /** Instantiates a basic cache object. */
254 Cache(const Params *p, TagStore *tags);
255
256 void regStats();
257
258 /**
259 * Performs the access specified by the request.
260 * @param pkt The request to perform.
261 * @return The result of the access.
262 */
263 bool timingAccess(PacketPtr pkt);
264
265 /**
266 * Performs the access specified by the request.
267 * @param pkt The request to perform.
268 * @return The result of the access.
269 */
270 Tick atomicAccess(PacketPtr pkt);
271
272 /**
273 * Performs the access specified by the request.
274 * @param pkt The request to perform.
275 * @param fromCpuSide from the CPU side port or the memory side port
276 */
277 void functionalAccess(PacketPtr pkt, bool fromCpuSide);
278
279 /**
280 * Handles a response (cache line fill/write ack) from the bus.
281 * @param pkt The request being responded to.
282 */
283 void handleResponse(PacketPtr pkt);
284
285 /**
286 * Snoops bus transactions to maintain coherence.
287 * @param pkt The current bus transaction.
288 */
289 void snoopTiming(PacketPtr pkt);
290
291 /**
292 * Snoop for the provided request in the cache and return the estimated
293 * time of completion.
294 * @param pkt The memory request to snoop
295 * @return The estimated completion time.
296 */
297 Tick snoopAtomic(PacketPtr pkt);
298
299 /**
300 * Squash all requests associated with specified thread.
301 * intended for use by I-cache.
302 * @param threadNum The thread to squash.
303 */
304 void squash(int threadNum);
305
306 /**
307 * Generate an appropriate downstream bus request packet for the
308 * given parameters.
309 * @param cpu_pkt The upstream request that needs to be satisfied.
310 * @param blk The block currently in the cache corresponding to
311 * cpu_pkt (NULL if none).
312 * @param needsExclusive Indicates that an exclusive copy is required
313 * even if the request in cpu_pkt doesn't indicate that.
314 * @return A new Packet containing the request, or NULL if the
315 * current request in cpu_pkt should just be forwarded on.
316 */
317 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
318 bool needsExclusive);
319
320 /**
321 * Return the next MSHR to service, either a pending miss from the
322 * mshrQueue, a buffered write from the write buffer, or something
323 * from the prefetcher. This function is responsible for
324 * prioritizing among those sources on the fly.
325 */
326 MSHR *getNextMSHR();
327
328 /**
329 * Selects an outstanding request to service. Called when the
330 * cache gets granted the downstream bus in timing mode.
331 * @return The request to service, NULL if none found.
332 */
333 PacketPtr getTimingPacket();
334
335 /**
336 * Marks a request as in service (sent on the bus). This can have side
337 * effect since storage for no response commands is deallocated once they
338 * are successfully sent.
339 * @param pkt The request that was sent on the bus.
340 */
341 void markInService(MSHR *mshr, PacketPtr pkt = 0);
342
343 /**
344 * Perform the given writeback request.
345 * @param pkt The writeback request.
346 */
347 void doWriteback(PacketPtr pkt);
348
349 /**
350 * Return whether there are any outstanding misses.
351 */
352 bool outstandingMisses() const
353 {
354 return mshrQueue.allocated != 0;
355 }
356
357 CacheBlk *findBlock(Addr addr) {
358 return tags->findBlock(addr);
359 }
360
361 bool inCache(Addr addr) {
362 return (tags->findBlock(addr) != 0);
363 }
364
365 bool inMissQueue(Addr addr) {
366 return (mshrQueue.findMatch(addr) != 0);
367 }
368
369 /**
370 * Find next request ready time from among possible sources.
371 */
372 Tick nextMSHRReadyTime();
373};
374
375#endif // __CACHE_HH__
|