1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 * Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/misc.hh" // fatal, panic, and warn
43
44#include "mem/cache/base.hh"
45#include "mem/cache/blk.hh"
46#include "mem/cache/mshr.hh"
47
48#include "sim/eventq.hh"
49
50//Forward decleration
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
57 */
58template <class TagStore>
59class Cache : public BaseCache
60{
61 public:
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64 /** A typedef for a list of BlkType pointers. */
65 typedef typename TagStore::BlkList BlkList;
66
67 bool prefetchAccess;
68
69 protected:
70
71 class CpuSidePort : public CachePort
72 {
73 public:
74 CpuSidePort(const std::string &_name,
75 Cache<TagStore> *_cache,
76 const std::string &_label,
77 std::vector<Range<Addr> > filterRanges);
78
79 // BaseCache::CachePort just has a BaseCache *; this function
80 // lets us get back the type info we lost when we stored the
81 // cache pointer there.
82 Cache<TagStore> *myCache() {
83 return static_cast<Cache<TagStore> *>(cache);
84 }
85
86 virtual void getDeviceAddressRanges(AddrRangeList &resp,
87 bool &snoop);
88
89 virtual bool recvTiming(PacketPtr pkt);
90
91 virtual Tick recvAtomic(PacketPtr pkt);
92
93 virtual void recvFunctional(PacketPtr pkt);
94 };
95
96 class MemSidePort : public CachePort
97 {
98 public:
99 MemSidePort(const std::string &_name,
100 Cache<TagStore> *_cache,
101 const std::string &_label,
102 std::vector<Range<Addr> > filterRanges);
103
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore> *myCache() {
108 return static_cast<Cache<TagStore> *>(cache);
109 }
110
111 void sendPacket();
112
113 void processSendEvent();
114
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
116 bool &snoop);
117
118 virtual bool recvTiming(PacketPtr pkt);
119
120 virtual void recvRetry();
121
122 virtual Tick recvAtomic(PacketPtr pkt);
123
124 virtual void recvFunctional(PacketPtr pkt);
125
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127 SendEvent;
128 };
129
130 /** Tag and data Storage */
131 TagStore *tags;
132
133 /** Prefetcher */
134 BasePrefetcher *prefetcher;
135
136 /** Temporary cache block for occasional transitory use */
137 BlkType *tempBlock;
138
139 /**
140 * Can this cache should allocate a block on a line-sized write miss.
141 */
142 const bool doFastWrites;
143
144 const bool prefetchMiss;
145
146 /**
147 * Handle a replacement for the given request.
148 * @param blk A pointer to the block, usually NULL
149 * @param pkt The memory request to satisfy.
150 * @param new_state The new state of the block.
151 * @param writebacks A list to store any generated writebacks.
152 */
153 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154 CacheBlk::State new_state, PacketList &writebacks);
155
156 /**
157 * Does all the processing necessary to perform the provided request.
158 * @param pkt The memory request to perform.
159 * @param lat The latency of the access.
160 * @param writebacks List for any writebacks that need to be performed.
161 * @param update True if the replacement data should be updated.
162 * @return Pointer to the cache block touched by the request. NULL if it
163 * was a miss.
164 */
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 * Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/misc.hh" // fatal, panic, and warn
43
44#include "mem/cache/base.hh"
45#include "mem/cache/blk.hh"
46#include "mem/cache/mshr.hh"
47
48#include "sim/eventq.hh"
49
50//Forward decleration
51class BasePrefetcher;
52
53/**
54 * A template-policy based cache. The behavior of the cache can be altered by
55 * supplying different template policies. TagStore handles all tag and data
56 * storage @sa TagStore.
57 */
58template <class TagStore>
59class Cache : public BaseCache
60{
61 public:
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64 /** A typedef for a list of BlkType pointers. */
65 typedef typename TagStore::BlkList BlkList;
66
67 bool prefetchAccess;
68
69 protected:
70
71 class CpuSidePort : public CachePort
72 {
73 public:
74 CpuSidePort(const std::string &_name,
75 Cache<TagStore> *_cache,
76 const std::string &_label,
77 std::vector<Range<Addr> > filterRanges);
78
79 // BaseCache::CachePort just has a BaseCache *; this function
80 // lets us get back the type info we lost when we stored the
81 // cache pointer there.
82 Cache<TagStore> *myCache() {
83 return static_cast<Cache<TagStore> *>(cache);
84 }
85
86 virtual void getDeviceAddressRanges(AddrRangeList &resp,
87 bool &snoop);
88
89 virtual bool recvTiming(PacketPtr pkt);
90
91 virtual Tick recvAtomic(PacketPtr pkt);
92
93 virtual void recvFunctional(PacketPtr pkt);
94 };
95
96 class MemSidePort : public CachePort
97 {
98 public:
99 MemSidePort(const std::string &_name,
100 Cache<TagStore> *_cache,
101 const std::string &_label,
102 std::vector<Range<Addr> > filterRanges);
103
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore> *myCache() {
108 return static_cast<Cache<TagStore> *>(cache);
109 }
110
111 void sendPacket();
112
113 void processSendEvent();
114
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
116 bool &snoop);
117
118 virtual bool recvTiming(PacketPtr pkt);
119
120 virtual void recvRetry();
121
122 virtual Tick recvAtomic(PacketPtr pkt);
123
124 virtual void recvFunctional(PacketPtr pkt);
125
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127 SendEvent;
128 };
129
130 /** Tag and data Storage */
131 TagStore *tags;
132
133 /** Prefetcher */
134 BasePrefetcher *prefetcher;
135
136 /** Temporary cache block for occasional transitory use */
137 BlkType *tempBlock;
138
139 /**
140 * Can this cache should allocate a block on a line-sized write miss.
141 */
142 const bool doFastWrites;
143
144 const bool prefetchMiss;
145
146 /**
147 * Handle a replacement for the given request.
148 * @param blk A pointer to the block, usually NULL
149 * @param pkt The memory request to satisfy.
150 * @param new_state The new state of the block.
151 * @param writebacks A list to store any generated writebacks.
152 */
153 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154 CacheBlk::State new_state, PacketList &writebacks);
155
156 /**
157 * Does all the processing necessary to perform the provided request.
158 * @param pkt The memory request to perform.
159 * @param lat The latency of the access.
160 * @param writebacks List for any writebacks that need to be performed.
161 * @param update True if the replacement data should be updated.
162 * @return Pointer to the cache block touched by the request. NULL if it
163 * was a miss.
164 */
|
166
167 /**
168 *Handle doing the Compare and Swap function for SPARC.
169 */
170 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
171
172 /**
173 * Find a block frame for new block at address addr, assuming that
174 * the block is not currently in the cache. Append writebacks if
175 * any to provided packet list. Return free block frame. May
176 * return NULL if there are no replaceable blocks at the moment.
177 */
178 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
179
180 /**
181 * Populates a cache block and handles all outstanding requests for the
182 * satisfied fill request. This version takes two memory requests. One
183 * contains the fill data, the other is an optional target to satisfy.
184 * Used for Cache::probe.
185 * @param pkt The memory request with the fill data.
186 * @param blk The cache block if it already exists.
187 * @param writebacks List for any writebacks that need to be performed.
188 * @return Pointer to the new cache block.
189 */
190 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
191 PacketList &writebacks);
192
193 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
194 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
195
196 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
197 bool already_copied, bool pending_inval);
198
199 /**
200 * Sets the blk to the new state.
201 * @param blk The cache block being snooped.
202 * @param new_state The new coherence state for the block.
203 */
204 void handleSnoop(PacketPtr ptk, BlkType *blk,
205 bool is_timing, bool is_deferred, bool pending_inval);
206
207 /**
208 * Create a writeback request for the given block.
209 * @param blk The block to writeback.
210 * @return The writeback request for the block.
211 */
212 PacketPtr writebackBlk(BlkType *blk);
213
214 public:
215 /** Instantiates a basic cache object. */
216 Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
217
218 virtual Port *getPort(const std::string &if_name, int idx = -1);
219 virtual void deletePortRefs(Port *p);
220
221 void regStats();
222
223 /**
224 * Performs the access specified by the request.
225 * @param pkt The request to perform.
226 * @return The result of the access.
227 */
228 bool timingAccess(PacketPtr pkt);
229
230 /**
231 * Performs the access specified by the request.
232 * @param pkt The request to perform.
233 * @return The result of the access.
234 */
235 Tick atomicAccess(PacketPtr pkt);
236
237 /**
238 * Performs the access specified by the request.
239 * @param pkt The request to perform.
240 * @return The result of the access.
241 */
242 void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
243 CachePort *otherSidePort);
244
245 /**
246 * Handles a response (cache line fill/write ack) from the bus.
247 * @param pkt The request being responded to.
248 */
249 void handleResponse(PacketPtr pkt);
250
251 /**
252 * Snoops bus transactions to maintain coherence.
253 * @param pkt The current bus transaction.
254 */
255 void snoopTiming(PacketPtr pkt);
256
257 /**
258 * Snoop for the provided request in the cache and return the estimated
259 * time of completion.
260 * @param pkt The memory request to snoop
261 * @return The estimated completion time.
262 */
263 Tick snoopAtomic(PacketPtr pkt);
264
265 /**
266 * Squash all requests associated with specified thread.
267 * intended for use by I-cache.
268 * @param threadNum The thread to squash.
269 */
270 void squash(int threadNum);
271
272 /**
273 * Generate an appropriate downstream bus request packet for the
274 * given parameters.
275 * @param cpu_pkt The upstream request that needs to be satisfied.
276 * @param blk The block currently in the cache corresponding to
277 * cpu_pkt (NULL if none).
278 * @param needsExclusive Indicates that an exclusive copy is required
279 * even if the request in cpu_pkt doesn't indicate that.
280 * @return A new Packet containing the request, or NULL if the
281 * current request in cpu_pkt should just be forwarded on.
282 */
283 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
284 bool needsExclusive);
285
286 /**
287 * Return the next MSHR to service, either a pending miss from the
288 * mshrQueue, a buffered write from the write buffer, or something
289 * from the prefetcher. This function is responsible for
290 * prioritizing among those sources on the fly.
291 */
292 MSHR *getNextMSHR();
293
294 /**
295 * Selects an outstanding request to service. Called when the
296 * cache gets granted the downstream bus in timing mode.
297 * @return The request to service, NULL if none found.
298 */
299 PacketPtr getTimingPacket();
300
301 /**
302 * Marks a request as in service (sent on the bus). This can have side
303 * effect since storage for no response commands is deallocated once they
304 * are successfully sent.
305 * @param pkt The request that was sent on the bus.
306 */
307 void markInService(MSHR *mshr);
308
309 /**
310 * Perform the given writeback request.
311 * @param pkt The writeback request.
312 */
313 void doWriteback(PacketPtr pkt);
314
315 /**
316 * Return whether there are any outstanding misses.
317 */
318 bool outstandingMisses() const
319 {
320 return mshrQueue.allocated != 0;
321 }
322
323 CacheBlk *findBlock(Addr addr) {
324 return tags->findBlock(addr);
325 }
326
327 bool inCache(Addr addr) {
328 return (tags->findBlock(addr) != 0);
329 }
330
331 bool inMissQueue(Addr addr) {
332 return (mshrQueue.findMatch(addr) != 0);
333 }
334};
335
336#endif // __CACHE_HH__
| 167
168 /**
169 *Handle doing the Compare and Swap function for SPARC.
170 */
171 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
172
173 /**
174 * Find a block frame for new block at address addr, assuming that
175 * the block is not currently in the cache. Append writebacks if
176 * any to provided packet list. Return free block frame. May
177 * return NULL if there are no replaceable blocks at the moment.
178 */
179 BlkType *allocateBlock(Addr addr, PacketList &writebacks);
180
181 /**
182 * Populates a cache block and handles all outstanding requests for the
183 * satisfied fill request. This version takes two memory requests. One
184 * contains the fill data, the other is an optional target to satisfy.
185 * Used for Cache::probe.
186 * @param pkt The memory request with the fill data.
187 * @param blk The cache block if it already exists.
188 * @param writebacks List for any writebacks that need to be performed.
189 * @return Pointer to the new cache block.
190 */
191 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
192 PacketList &writebacks);
193
194 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
195 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
196
197 void doTimingSupplyResponse(PacketPtr req_pkt, uint8_t *blk_data,
198 bool already_copied, bool pending_inval);
199
200 /**
201 * Sets the blk to the new state.
202 * @param blk The cache block being snooped.
203 * @param new_state The new coherence state for the block.
204 */
205 void handleSnoop(PacketPtr ptk, BlkType *blk,
206 bool is_timing, bool is_deferred, bool pending_inval);
207
208 /**
209 * Create a writeback request for the given block.
210 * @param blk The block to writeback.
211 * @return The writeback request for the block.
212 */
213 PacketPtr writebackBlk(BlkType *blk);
214
215 public:
216 /** Instantiates a basic cache object. */
217 Cache(const Params *p, TagStore *tags, BasePrefetcher *prefetcher);
218
219 virtual Port *getPort(const std::string &if_name, int idx = -1);
220 virtual void deletePortRefs(Port *p);
221
222 void regStats();
223
224 /**
225 * Performs the access specified by the request.
226 * @param pkt The request to perform.
227 * @return The result of the access.
228 */
229 bool timingAccess(PacketPtr pkt);
230
231 /**
232 * Performs the access specified by the request.
233 * @param pkt The request to perform.
234 * @return The result of the access.
235 */
236 Tick atomicAccess(PacketPtr pkt);
237
238 /**
239 * Performs the access specified by the request.
240 * @param pkt The request to perform.
241 * @return The result of the access.
242 */
243 void functionalAccess(PacketPtr pkt, CachePort *incomingPort,
244 CachePort *otherSidePort);
245
246 /**
247 * Handles a response (cache line fill/write ack) from the bus.
248 * @param pkt The request being responded to.
249 */
250 void handleResponse(PacketPtr pkt);
251
252 /**
253 * Snoops bus transactions to maintain coherence.
254 * @param pkt The current bus transaction.
255 */
256 void snoopTiming(PacketPtr pkt);
257
258 /**
259 * Snoop for the provided request in the cache and return the estimated
260 * time of completion.
261 * @param pkt The memory request to snoop
262 * @return The estimated completion time.
263 */
264 Tick snoopAtomic(PacketPtr pkt);
265
266 /**
267 * Squash all requests associated with specified thread.
268 * intended for use by I-cache.
269 * @param threadNum The thread to squash.
270 */
271 void squash(int threadNum);
272
273 /**
274 * Generate an appropriate downstream bus request packet for the
275 * given parameters.
276 * @param cpu_pkt The upstream request that needs to be satisfied.
277 * @param blk The block currently in the cache corresponding to
278 * cpu_pkt (NULL if none).
279 * @param needsExclusive Indicates that an exclusive copy is required
280 * even if the request in cpu_pkt doesn't indicate that.
281 * @return A new Packet containing the request, or NULL if the
282 * current request in cpu_pkt should just be forwarded on.
283 */
284 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
285 bool needsExclusive);
286
287 /**
288 * Return the next MSHR to service, either a pending miss from the
289 * mshrQueue, a buffered write from the write buffer, or something
290 * from the prefetcher. This function is responsible for
291 * prioritizing among those sources on the fly.
292 */
293 MSHR *getNextMSHR();
294
295 /**
296 * Selects an outstanding request to service. Called when the
297 * cache gets granted the downstream bus in timing mode.
298 * @return The request to service, NULL if none found.
299 */
300 PacketPtr getTimingPacket();
301
302 /**
303 * Marks a request as in service (sent on the bus). This can have side
304 * effect since storage for no response commands is deallocated once they
305 * are successfully sent.
306 * @param pkt The request that was sent on the bus.
307 */
308 void markInService(MSHR *mshr);
309
310 /**
311 * Perform the given writeback request.
312 * @param pkt The writeback request.
313 */
314 void doWriteback(PacketPtr pkt);
315
316 /**
317 * Return whether there are any outstanding misses.
318 */
319 bool outstandingMisses() const
320 {
321 return mshrQueue.allocated != 0;
322 }
323
324 CacheBlk *findBlock(Addr addr) {
325 return tags->findBlock(addr);
326 }
327
328 bool inCache(Addr addr) {
329 return (tags->findBlock(addr) != 0);
330 }
331
332 bool inMissQueue(Addr addr) {
333 return (mshrQueue.findMatch(addr) != 0);
334 }
335};
336
337#endif // __CACHE_HH__
|