1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 * Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/compression/base.hh"
43#include "base/misc.hh" // fatal, panic, and warn
44#include "cpu/smt.hh" // SMT_MAX_THREADS
45
46#include "mem/cache/base_cache.hh"
47#include "mem/cache/cache_blk.hh"
48#include "mem/cache/miss/mshr.hh"
49
50#include "sim/eventq.hh"
51
52//Forward decleration
53class BasePrefetcher;
54
55/**
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.
61 */
62template <class TagStore, class Coherence>
63class Cache : public BaseCache
64{
65 public:
66 /** Define the type of cache block to use. */
67 typedef typename TagStore::BlkType BlkType;
68 /** A typedef for a list of BlkType pointers. */
69 typedef typename TagStore::BlkList BlkList;
70
71 bool prefetchAccess;
72
73 protected:
74
75 class CpuSidePort : public CachePort
76 {
77 public:
78 CpuSidePort(const std::string &_name,
79 Cache<TagStore,Coherence> *_cache);
80
81 // BaseCache::CachePort just has a BaseCache *; this function
82 // lets us get back the type info we lost when we stored the
83 // cache pointer there.
84 Cache<TagStore,Coherence> *myCache() {
85 return static_cast<Cache<TagStore,Coherence> *>(cache);
86 }
87
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
89 bool &snoop);
90
91 virtual bool recvTiming(PacketPtr pkt);
92
93 virtual Tick recvAtomic(PacketPtr pkt);
94
95 virtual void recvFunctional(PacketPtr pkt);
96 };
97
98 class MemSidePort : public CachePort
99 {
100 public:
101 MemSidePort(const std::string &_name,
102 Cache<TagStore,Coherence> *_cache);
103
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore,Coherence> *myCache() {
108 return static_cast<Cache<TagStore,Coherence> *>(cache);
109 }
110
111 void sendPacket();
112
113 void processSendEvent();
114
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
116 bool &snoop);
117
118 virtual bool recvTiming(PacketPtr pkt);
119
120 virtual void recvRetry();
121
122 virtual Tick recvAtomic(PacketPtr pkt);
123
124 virtual void recvFunctional(PacketPtr pkt);
125
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127 SendEvent;
128 };
129
130 /** Tag and data Storage */
131 TagStore *tags;
132
133 /** Coherence protocol. */
134 Coherence *coherence;
135
136 /** Prefetcher */
137 BasePrefetcher *prefetcher;
138
139 /**
140 * Can this cache should allocate a block on a line-sized write miss.
141 */
142 const bool doFastWrites;
143
144 const bool prefetchMiss;
145
146 /**
147 * Handle a replacement for the given request.
148 * @param blk A pointer to the block, usually NULL
149 * @param pkt The memory request to satisfy.
150 * @param new_state The new state of the block.
151 * @param writebacks A list to store any generated writebacks.
152 */
153 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154 CacheBlk::State new_state, PacketList &writebacks);
155
156 /**
157 * Does all the processing necessary to perform the provided request.
158 * @param pkt The memory request to perform.
159 * @param lat The latency of the access.
160 * @param writebacks List for any writebacks that need to be performed.
161 * @param update True if the replacement data should be updated.
162 * @return Pointer to the cache block touched by the request. NULL if it
163 * was a miss.
164 */
165 bool access(PacketPtr pkt, BlkType *&blk, int &lat);
166
167 /**
168 *Handle doing the Compare and Swap function for SPARC.
169 */
170 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
171
172 /**
173 * Populates a cache block and handles all outstanding requests for the
174 * satisfied fill request. This version takes two memory requests. One
175 * contains the fill data, the other is an optional target to satisfy.
176 * Used for Cache::probe.
177 * @param pkt The memory request with the fill data.
178 * @param blk The cache block if it already exists.
179 * @param writebacks List for any writebacks that need to be performed.
180 * @return Pointer to the new cache block.
181 */
182 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
183 PacketList &writebacks);
184
185 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
186 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
187
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 * Ron Dreslinski
32 */
33
34/**
35 * @file
36 * Describes a cache based on template policies.
37 */
38
39#ifndef __CACHE_HH__
40#define __CACHE_HH__
41
42#include "base/compression/base.hh"
43#include "base/misc.hh" // fatal, panic, and warn
44#include "cpu/smt.hh" // SMT_MAX_THREADS
45
46#include "mem/cache/base_cache.hh"
47#include "mem/cache/cache_blk.hh"
48#include "mem/cache/miss/mshr.hh"
49
50#include "sim/eventq.hh"
51
52//Forward decleration
53class BasePrefetcher;
54
55/**
56 * A template-policy based cache. The behavior of the cache can be altered by
57 * supplying different template policies. TagStore handles all tag and data
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
59 * @sa MissQueue. Coherence handles all coherence policy details @sa
60 * UniCoherence, SimpleMultiCoherence.
61 */
62template <class TagStore, class Coherence>
63class Cache : public BaseCache
64{
65 public:
66 /** Define the type of cache block to use. */
67 typedef typename TagStore::BlkType BlkType;
68 /** A typedef for a list of BlkType pointers. */
69 typedef typename TagStore::BlkList BlkList;
70
71 bool prefetchAccess;
72
73 protected:
74
75 class CpuSidePort : public CachePort
76 {
77 public:
78 CpuSidePort(const std::string &_name,
79 Cache<TagStore,Coherence> *_cache);
80
81 // BaseCache::CachePort just has a BaseCache *; this function
82 // lets us get back the type info we lost when we stored the
83 // cache pointer there.
84 Cache<TagStore,Coherence> *myCache() {
85 return static_cast<Cache<TagStore,Coherence> *>(cache);
86 }
87
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
89 bool &snoop);
90
91 virtual bool recvTiming(PacketPtr pkt);
92
93 virtual Tick recvAtomic(PacketPtr pkt);
94
95 virtual void recvFunctional(PacketPtr pkt);
96 };
97
98 class MemSidePort : public CachePort
99 {
100 public:
101 MemSidePort(const std::string &_name,
102 Cache<TagStore,Coherence> *_cache);
103
104 // BaseCache::CachePort just has a BaseCache *; this function
105 // lets us get back the type info we lost when we stored the
106 // cache pointer there.
107 Cache<TagStore,Coherence> *myCache() {
108 return static_cast<Cache<TagStore,Coherence> *>(cache);
109 }
110
111 void sendPacket();
112
113 void processSendEvent();
114
115 virtual void getDeviceAddressRanges(AddrRangeList &resp,
116 bool &snoop);
117
118 virtual bool recvTiming(PacketPtr pkt);
119
120 virtual void recvRetry();
121
122 virtual Tick recvAtomic(PacketPtr pkt);
123
124 virtual void recvFunctional(PacketPtr pkt);
125
126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent>
127 SendEvent;
128 };
129
130 /** Tag and data Storage */
131 TagStore *tags;
132
133 /** Coherence protocol. */
134 Coherence *coherence;
135
136 /** Prefetcher */
137 BasePrefetcher *prefetcher;
138
139 /**
140 * Can this cache should allocate a block on a line-sized write miss.
141 */
142 const bool doFastWrites;
143
144 const bool prefetchMiss;
145
146 /**
147 * Handle a replacement for the given request.
148 * @param blk A pointer to the block, usually NULL
149 * @param pkt The memory request to satisfy.
150 * @param new_state The new state of the block.
151 * @param writebacks A list to store any generated writebacks.
152 */
153 BlkType* doReplacement(BlkType *blk, PacketPtr pkt,
154 CacheBlk::State new_state, PacketList &writebacks);
155
156 /**
157 * Does all the processing necessary to perform the provided request.
158 * @param pkt The memory request to perform.
159 * @param lat The latency of the access.
160 * @param writebacks List for any writebacks that need to be performed.
161 * @param update True if the replacement data should be updated.
162 * @return Pointer to the cache block touched by the request. NULL if it
163 * was a miss.
164 */
165 bool access(PacketPtr pkt, BlkType *&blk, int &lat);
166
167 /**
168 *Handle doing the Compare and Swap function for SPARC.
169 */
170 void cmpAndSwap(BlkType *blk, PacketPtr pkt);
171
172 /**
173 * Populates a cache block and handles all outstanding requests for the
174 * satisfied fill request. This version takes two memory requests. One
175 * contains the fill data, the other is an optional target to satisfy.
176 * Used for Cache::probe.
177 * @param pkt The memory request with the fill data.
178 * @param blk The cache block if it already exists.
179 * @param writebacks List for any writebacks that need to be performed.
180 * @return Pointer to the new cache block.
181 */
182 BlkType *handleFill(PacketPtr pkt, BlkType *blk,
183 PacketList &writebacks);
184
185 void satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk);
186 bool satisfyMSHR(MSHR *mshr, PacketPtr pkt, BlkType *blk);
187
|
196
197 /**
198 * Create a writeback request for the given block.
199 * @param blk The block to writeback.
200 * @return The writeback request for the block.
201 */
202 PacketPtr writebackBlk(BlkType *blk);
203
204 public:
205
206 class Params
207 {
208 public:
209 TagStore *tags;
210 Coherence *coherence;
211 BaseCache::Params baseParams;
212 BasePrefetcher*prefetcher;
213 bool prefetchAccess;
214 const bool doFastWrites;
215 const bool prefetchMiss;
216
217 Params(TagStore *_tags, Coherence *coh,
218 BaseCache::Params params,
219 BasePrefetcher *_prefetcher,
220 bool prefetch_access, int hit_latency,
221 bool do_fast_writes,
222 bool prefetch_miss)
223 : tags(_tags), coherence(coh),
224 baseParams(params),
225 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
226 doFastWrites(do_fast_writes),
227 prefetchMiss(prefetch_miss)
228 {
229 }
230 };
231
232 /** Instantiates a basic cache object. */
233 Cache(const std::string &_name, Params ¶ms);
234
235 virtual Port *getPort(const std::string &if_name, int idx = -1);
236 virtual void deletePortRefs(Port *p);
237
238 void regStats();
239
240 /**
241 * Performs the access specified by the request.
242 * @param pkt The request to perform.
243 * @return The result of the access.
244 */
245 bool timingAccess(PacketPtr pkt);
246
247 /**
248 * Performs the access specified by the request.
249 * @param pkt The request to perform.
250 * @return The result of the access.
251 */
252 Tick atomicAccess(PacketPtr pkt);
253
254 /**
255 * Performs the access specified by the request.
256 * @param pkt The request to perform.
257 * @return The result of the access.
258 */
259 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
260
261 /**
262 * Handles a response (cache line fill/write ack) from the bus.
263 * @param pkt The request being responded to.
264 */
265 void handleResponse(PacketPtr pkt);
266
267 /**
268 * Snoops bus transactions to maintain coherence.
269 * @param pkt The current bus transaction.
270 */
271 void snoopTiming(PacketPtr pkt);
272
273 /**
274 * Snoop for the provided request in the cache and return the estimated
275 * time of completion.
276 * @param pkt The memory request to snoop
277 * @return The estimated completion time.
278 */
279 Tick snoopAtomic(PacketPtr pkt);
280
281 /**
282 * Squash all requests associated with specified thread.
283 * intended for use by I-cache.
284 * @param threadNum The thread to squash.
285 */
286 void squash(int threadNum);
287
288 /**
289 * Selects a outstanding request to service.
290 * @return The request to service, NULL if none found.
291 */
292 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
293 bool needsExclusive);
294 MSHR *getNextMSHR();
295 PacketPtr getTimingPacket();
296
297 /**
298 * Marks a request as in service (sent on the bus). This can have side
299 * effect since storage for no response commands is deallocated once they
300 * are successfully sent.
301 * @param pkt The request that was sent on the bus.
302 */
303 void markInService(MSHR *mshr);
304
305 /**
306 * Perform the given writeback request.
307 * @param pkt The writeback request.
308 */
309 void doWriteback(PacketPtr pkt);
310
311 /**
312 * Return whether there are any outstanding misses.
313 */
314 bool outstandingMisses() const
315 {
316 return mshrQueue.allocated != 0;
317 }
318
319 CacheBlk *findBlock(Addr addr) {
320 return tags->findBlock(addr);
321 }
322
323 bool inCache(Addr addr) {
324 return (tags->findBlock(addr) != 0);
325 }
326
327 bool inMissQueue(Addr addr) {
328 return (mshrQueue.findMatch(addr) != 0);
329 }
330};
331
332#endif // __CACHE_HH__
| 198
199 /**
200 * Create a writeback request for the given block.
201 * @param blk The block to writeback.
202 * @return The writeback request for the block.
203 */
204 PacketPtr writebackBlk(BlkType *blk);
205
206 public:
207
208 class Params
209 {
210 public:
211 TagStore *tags;
212 Coherence *coherence;
213 BaseCache::Params baseParams;
214 BasePrefetcher*prefetcher;
215 bool prefetchAccess;
216 const bool doFastWrites;
217 const bool prefetchMiss;
218
219 Params(TagStore *_tags, Coherence *coh,
220 BaseCache::Params params,
221 BasePrefetcher *_prefetcher,
222 bool prefetch_access, int hit_latency,
223 bool do_fast_writes,
224 bool prefetch_miss)
225 : tags(_tags), coherence(coh),
226 baseParams(params),
227 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
228 doFastWrites(do_fast_writes),
229 prefetchMiss(prefetch_miss)
230 {
231 }
232 };
233
234 /** Instantiates a basic cache object. */
235 Cache(const std::string &_name, Params ¶ms);
236
237 virtual Port *getPort(const std::string &if_name, int idx = -1);
238 virtual void deletePortRefs(Port *p);
239
240 void regStats();
241
242 /**
243 * Performs the access specified by the request.
244 * @param pkt The request to perform.
245 * @return The result of the access.
246 */
247 bool timingAccess(PacketPtr pkt);
248
249 /**
250 * Performs the access specified by the request.
251 * @param pkt The request to perform.
252 * @return The result of the access.
253 */
254 Tick atomicAccess(PacketPtr pkt);
255
256 /**
257 * Performs the access specified by the request.
258 * @param pkt The request to perform.
259 * @return The result of the access.
260 */
261 void functionalAccess(PacketPtr pkt, CachePort *otherSidePort);
262
263 /**
264 * Handles a response (cache line fill/write ack) from the bus.
265 * @param pkt The request being responded to.
266 */
267 void handleResponse(PacketPtr pkt);
268
269 /**
270 * Snoops bus transactions to maintain coherence.
271 * @param pkt The current bus transaction.
272 */
273 void snoopTiming(PacketPtr pkt);
274
275 /**
276 * Snoop for the provided request in the cache and return the estimated
277 * time of completion.
278 * @param pkt The memory request to snoop
279 * @return The estimated completion time.
280 */
281 Tick snoopAtomic(PacketPtr pkt);
282
283 /**
284 * Squash all requests associated with specified thread.
285 * intended for use by I-cache.
286 * @param threadNum The thread to squash.
287 */
288 void squash(int threadNum);
289
290 /**
291 * Selects a outstanding request to service.
292 * @return The request to service, NULL if none found.
293 */
294 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
295 bool needsExclusive);
296 MSHR *getNextMSHR();
297 PacketPtr getTimingPacket();
298
299 /**
300 * Marks a request as in service (sent on the bus). This can have side
301 * effect since storage for no response commands is deallocated once they
302 * are successfully sent.
303 * @param pkt The request that was sent on the bus.
304 */
305 void markInService(MSHR *mshr);
306
307 /**
308 * Perform the given writeback request.
309 * @param pkt The writeback request.
310 */
311 void doWriteback(PacketPtr pkt);
312
313 /**
314 * Return whether there are any outstanding misses.
315 */
316 bool outstandingMisses() const
317 {
318 return mshrQueue.allocated != 0;
319 }
320
321 CacheBlk *findBlock(Addr addr) {
322 return tags->findBlock(addr);
323 }
324
325 bool inCache(Addr addr) {
326 return (tags->findBlock(addr) != 0);
327 }
328
329 bool inMissQueue(Addr addr) {
330 return (mshrQueue.findMatch(addr) != 0);
331 }
332};
333
334#endif // __CACHE_HH__
|