1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/miss/miss_buffer.hh"
46#include "mem/cache/prefetch/prefetcher.hh"
47
48//Forward decleration
49class MSHR;
50
51
52/**
53 * A template-policy based cache. The behavior of the cache can be altered by
54 * supplying different template policies. TagStore handles all tag and data
55 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
56 * @sa MissQueue. Coherence handles all coherence policy details @sa
57 * UniCoherence, SimpleMultiCoherence.
58 */
59template <class TagStore, class Coherence>
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/miss/miss_buffer.hh"
46#include "mem/cache/prefetch/prefetcher.hh"
47
48//Forward decleration
49class MSHR;
50
51
52/**
53 * A template-policy based cache. The behavior of the cache can be altered by
54 * supplying different template policies. TagStore handles all tag and data
55 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
56 * @sa MissQueue. Coherence handles all coherence policy details @sa
57 * UniCoherence, SimpleMultiCoherence.
58 */
59template <class TagStore, class Coherence>
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
|
| 67
|
67 protected:
68
| 68 protected:
69
|
| 70 class CpuSidePort : public CachePort
71 {
72 public:
73 CpuSidePort(const std::string &_name,
74 Cache<TagStore,Coherence> *_cache);
75
76 // BaseCache::CachePort just has a BaseCache *; this function
77 // lets us get back the type info we lost when we stored the
78 // cache pointer there.
79 Cache<TagStore,Coherence> *myCache() {
80 return static_cast<Cache<TagStore,Coherence> *>(cache);
81 }
82
83 virtual bool recvTiming(PacketPtr pkt);
84
85 virtual Tick recvAtomic(PacketPtr pkt);
86
87 virtual void recvFunctional(PacketPtr pkt);
88 };
89
90 class MemSidePort : public CachePort
91 {
92 public:
93 MemSidePort(const std::string &_name,
94 Cache<TagStore,Coherence> *_cache);
95
96 // BaseCache::CachePort just has a BaseCache *; this function
97 // lets us get back the type info we lost when we stored the
98 // cache pointer there.
99 Cache<TagStore,Coherence> *myCache() {
100 return static_cast<Cache<TagStore,Coherence> *>(cache);
101 }
102
103 virtual bool recvTiming(PacketPtr pkt);
104
105 virtual Tick recvAtomic(PacketPtr pkt);
106
107 virtual void recvFunctional(PacketPtr pkt);
108 };
109
|
69 /** Tag and data Storage */
70 TagStore *tags;
71 /** Miss and Writeback handler */
72 MissBuffer *missQueue;
73 /** Coherence protocol. */
74 Coherence *coherence;
75
76 /** Prefetcher */
77 Prefetcher<TagStore> *prefetcher;
78
79 /**
80 * The clock ratio of the outgoing bus.
81 * Used for calculating critical word first.
82 */
83 int busRatio;
84
85 /**
86 * The bus width in bytes of the outgoing bus.
87 * Used for calculating critical word first.
88 */
89 int busWidth;
90
91 /**
92 * The latency of a hit in this device.
93 */
94 int hitLatency;
95
96 /**
97 * A permanent mem req to always be used to cause invalidations.
98 * Used to append to target list, to cause an invalidation.
99 */
100 PacketPtr invalidatePkt;
101 Request *invalidateReq;
102
103 public:
104
105 class Params
106 {
107 public:
108 TagStore *tags;
109 MissBuffer *missQueue;
110 Coherence *coherence;
111 BaseCache::Params baseParams;
112 Prefetcher<TagStore> *prefetcher;
113 bool prefetchAccess;
114 int hitLatency;
115
116 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
117 BaseCache::Params params,
118 Prefetcher<TagStore> *_prefetcher,
119 bool prefetch_access, int hit_latency)
120 : tags(_tags), missQueue(mq), coherence(coh),
121 baseParams(params),
122 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
123 hitLatency(hit_latency)
124 {
125 }
126 };
127
128 /** Instantiates a basic cache object. */
129 Cache(const std::string &_name, Params ¶ms);
130
| 110 /** Tag and data Storage */
111 TagStore *tags;
112 /** Miss and Writeback handler */
113 MissBuffer *missQueue;
114 /** Coherence protocol. */
115 Coherence *coherence;
116
117 /** Prefetcher */
118 Prefetcher<TagStore> *prefetcher;
119
120 /**
121 * The clock ratio of the outgoing bus.
122 * Used for calculating critical word first.
123 */
124 int busRatio;
125
126 /**
127 * The bus width in bytes of the outgoing bus.
128 * Used for calculating critical word first.
129 */
130 int busWidth;
131
132 /**
133 * The latency of a hit in this device.
134 */
135 int hitLatency;
136
137 /**
138 * A permanent mem req to always be used to cause invalidations.
139 * Used to append to target list, to cause an invalidation.
140 */
141 PacketPtr invalidatePkt;
142 Request *invalidateReq;
143
144 public:
145
146 class Params
147 {
148 public:
149 TagStore *tags;
150 MissBuffer *missQueue;
151 Coherence *coherence;
152 BaseCache::Params baseParams;
153 Prefetcher<TagStore> *prefetcher;
154 bool prefetchAccess;
155 int hitLatency;
156
157 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
158 BaseCache::Params params,
159 Prefetcher<TagStore> *_prefetcher,
160 bool prefetch_access, int hit_latency)
161 : tags(_tags), missQueue(mq), coherence(coh),
162 baseParams(params),
163 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
164 hitLatency(hit_latency)
165 {
166 }
167 };
168
169 /** Instantiates a basic cache object. */
170 Cache(const std::string &_name, Params ¶ms);
171
|
131 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
132 bool isCpuSide);
| 172 virtual Port *getPort(const std::string &if_name, int idx = -1);
|
133
| 173
|
134 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
135
136 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
137
| |
138 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
139
140 void regStats();
141
142 /**
143 * Performs the access specified by the request.
144 * @param pkt The request to perform.
145 * @return The result of the access.
146 */
147 bool access(PacketPtr &pkt);
148
149 /**
150 * Selects a request to send on the bus.
151 * @return The memory request to service.
152 */
153 virtual PacketPtr getPacket();
154
155 /**
156 * Was the request was sent successfully?
157 * @param pkt The request.
158 * @param success True if the request was sent successfully.
159 */
160 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
161
162 /**
163 * Was the CSHR request was sent successfully?
164 * @param pkt The request.
165 * @param success True if the request was sent successfully.
166 */
167 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
168
169 /**
170 * Handles a response (cache line fill/write ack) from the bus.
171 * @param pkt The request being responded to.
172 */
173 void handleResponse(PacketPtr &pkt);
174
175 /**
176 * Selects a coherence message to forward to lower levels of the hierarchy.
177 * @return The coherence message to forward.
178 */
179 virtual PacketPtr getCoherencePacket();
180
181 /**
182 * Snoops bus transactions to maintain coherence.
183 * @param pkt The current bus transaction.
184 */
185 void snoop(PacketPtr &pkt);
186
187 void snoopResponse(PacketPtr &pkt);
188
189 /**
190 * Invalidates the block containing address if found.
191 * @param addr The address to look for.
192 * @param asid The address space ID of the address.
193 * @todo Is this function necessary?
194 */
195 void invalidateBlk(Addr addr);
196
197 /**
198 * Squash all requests associated with specified thread.
199 * intended for use by I-cache.
200 * @param threadNum The thread to squash.
201 */
202 void squash(int threadNum)
203 {
204 missQueue->squash(threadNum);
205 }
206
207 /**
208 * Return the number of outstanding misses in a Cache.
209 * Default returns 0.
210 *
211 * @retval unsigned The number of missing still outstanding.
212 */
213 unsigned outstandingMisses() const
214 {
215 return missQueue->getMisses();
216 }
217
218 /**
219 * Perform the access specified in the request and return the estimated
220 * time of completion. This function can either update the hierarchy state
221 * or just perform the access wherever the data is found depending on the
222 * state of the update flag.
223 * @param pkt The memory request to satisfy
224 * @param update If true, update the hierarchy, otherwise just perform the
225 * request.
226 * @return The estimated completion time.
227 */
228 Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
229
230 /**
231 * Snoop for the provided request in the cache and return the estimated
232 * time of completion.
233 * @todo Can a snoop probe not change state?
234 * @param pkt The memory request to satisfy
235 * @param update If true, update the hierarchy, otherwise just perform the
236 * request.
237 * @return The estimated completion time.
238 */
239 Tick snoopProbe(PacketPtr &pkt);
240};
241
242#endif // __CACHE_HH__
| 174 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
175
176 void regStats();
177
178 /**
179 * Performs the access specified by the request.
180 * @param pkt The request to perform.
181 * @return The result of the access.
182 */
183 bool access(PacketPtr &pkt);
184
185 /**
186 * Selects a request to send on the bus.
187 * @return The memory request to service.
188 */
189 virtual PacketPtr getPacket();
190
191 /**
192 * Was the request was sent successfully?
193 * @param pkt The request.
194 * @param success True if the request was sent successfully.
195 */
196 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
197
198 /**
199 * Was the CSHR request was sent successfully?
200 * @param pkt The request.
201 * @param success True if the request was sent successfully.
202 */
203 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
204
205 /**
206 * Handles a response (cache line fill/write ack) from the bus.
207 * @param pkt The request being responded to.
208 */
209 void handleResponse(PacketPtr &pkt);
210
211 /**
212 * Selects a coherence message to forward to lower levels of the hierarchy.
213 * @return The coherence message to forward.
214 */
215 virtual PacketPtr getCoherencePacket();
216
217 /**
218 * Snoops bus transactions to maintain coherence.
219 * @param pkt The current bus transaction.
220 */
221 void snoop(PacketPtr &pkt);
222
223 void snoopResponse(PacketPtr &pkt);
224
225 /**
226 * Invalidates the block containing address if found.
227 * @param addr The address to look for.
228 * @param asid The address space ID of the address.
229 * @todo Is this function necessary?
230 */
231 void invalidateBlk(Addr addr);
232
233 /**
234 * Squash all requests associated with specified thread.
235 * intended for use by I-cache.
236 * @param threadNum The thread to squash.
237 */
238 void squash(int threadNum)
239 {
240 missQueue->squash(threadNum);
241 }
242
243 /**
244 * Return the number of outstanding misses in a Cache.
245 * Default returns 0.
246 *
247 * @retval unsigned The number of missing still outstanding.
248 */
249 unsigned outstandingMisses() const
250 {
251 return missQueue->getMisses();
252 }
253
254 /**
255 * Perform the access specified in the request and return the estimated
256 * time of completion. This function can either update the hierarchy state
257 * or just perform the access wherever the data is found depending on the
258 * state of the update flag.
259 * @param pkt The memory request to satisfy
260 * @param update If true, update the hierarchy, otherwise just perform the
261 * request.
262 * @return The estimated completion time.
263 */
264 Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
265
266 /**
267 * Snoop for the provided request in the cache and return the estimated
268 * time of completion.
269 * @todo Can a snoop probe not change state?
270 * @param pkt The memory request to satisfy
271 * @param update If true, update the hierarchy, otherwise just perform the
272 * request.
273 * @return The estimated completion time.
274 */
275 Tick snoopProbe(PacketPtr &pkt);
276};
277
278#endif // __CACHE_HH__
|