1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
|
| 45#include "mem/cache/miss/miss_buffer.hh"
|
45#include "mem/cache/prefetch/prefetcher.hh"
46
47//Forward decleration
48class MSHR;
49
50
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */
| 46#include "mem/cache/prefetch/prefetcher.hh"
47
48//Forward decleration
49class MSHR;
50
51
52/**
53 * A template-policy based cache. The behavior of the cache can be altered by
54 * supplying different template policies. TagStore handles all tag and data
55 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
56 * @sa MissQueue. Coherence handles all coherence policy details @sa
57 * UniCoherence, SimpleMultiCoherence.
58 */
|
58template <class TagStore, class Buffering, class Coherence>
| 59template
|
59class Cache : public BaseCache
60{
61 public:
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64
65 bool prefetchAccess;
66 protected:
67
68 /** Tag and data Storage */
69 TagStore *tags;
70 /** Miss and Writeback handler */
| 60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
67 protected:
68
69 /** Tag and data Storage */
70 TagStore *tags;
71 /** Miss and Writeback handler */
|
71 Buffering *missQueue;
| 72 MissBuffer *missQueue;
|
72 /** Coherence protocol. */
73 Coherence *coherence;
74
75 /** Prefetcher */
| 73 /** Coherence protocol. */
74 Coherence *coherence;
75
76 /** Prefetcher */
|
76 Prefetcher<TagStore, Buffering> *prefetcher;
| 77 Prefetcher *prefetcher;
|
77
78 /**
79 * The clock ratio of the outgoing bus.
80 * Used for calculating critical word first.
81 */
82 int busRatio;
83
84 /**
85 * The bus width in bytes of the outgoing bus.
86 * Used for calculating critical word first.
87 */
88 int busWidth;
89
90 /**
91 * The latency of a hit in this device.
92 */
93 int hitLatency;
94
95 /**
96 * A permanent mem req to always be used to cause invalidations.
97 * Used to append to target list, to cause an invalidation.
98 */
99 PacketPtr invalidatePkt;
100 Request *invalidateReq;
101
102 public:
103
104 class Params
105 {
106 public:
107 TagStore *tags;
| 78
79 /**
80 * The clock ratio of the outgoing bus.
81 * Used for calculating critical word first.
82 */
83 int busRatio;
84
85 /**
86 * The bus width in bytes of the outgoing bus.
87 * Used for calculating critical word first.
88 */
89 int busWidth;
90
91 /**
92 * The latency of a hit in this device.
93 */
94 int hitLatency;
95
96 /**
97 * A permanent mem req to always be used to cause invalidations.
98 * Used to append to target list, to cause an invalidation.
99 */
100 PacketPtr invalidatePkt;
101 Request *invalidateReq;
102
103 public:
104
105 class Params
106 {
107 public:
108 TagStore *tags;
|
108 Buffering *missQueue;
| 109 MissBuffer *missQueue;
|
109 Coherence *coherence;
110 BaseCache::Params baseParams;
| 110 Coherence *coherence;
111 BaseCache::Params baseParams;
|
111 Prefetcher<TagStore, Buffering> *prefetcher;
| 112 Prefetcher *prefetcher;
|
112 bool prefetchAccess;
113 int hitLatency;
114
| 113 bool prefetchAccess;
114 int hitLatency;
115
|
115 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
| 116 Params(TagStore *_tags, MissBuffer *mq, Coherence *coh,
|
116 BaseCache::Params params,
| 117 BaseCache::Params params,
|
117 Prefetcher<TagStore, Buffering> *_prefetcher,
| 118 Prefetcher *_prefetcher,
|
118 bool prefetch_access, int hit_latency)
119 : tags(_tags), missQueue(mq), coherence(coh),
120 baseParams(params),
121 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
122 hitLatency(hit_latency)
123 {
124 }
125 };
126
127 /** Instantiates a basic cache object. */
128 Cache(const std::string &_name, Params ¶ms);
129
130 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
131 bool isCpuSide);
132
133 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
134
135 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
136
137 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
138
139 void regStats();
140
141 /**
142 * Performs the access specified by the request.
143 * @param pkt The request to perform.
144 * @return The result of the access.
145 */
146 bool access(PacketPtr &pkt);
147
148 /**
149 * Selects a request to send on the bus.
150 * @return The memory request to service.
151 */
152 virtual PacketPtr getPacket();
153
154 /**
155 * Was the request was sent successfully?
156 * @param pkt The request.
157 * @param success True if the request was sent successfully.
158 */
159 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
160
161 /**
162 * Was the CSHR request was sent successfully?
163 * @param pkt The request.
164 * @param success True if the request was sent successfully.
165 */
166 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
167
168 /**
169 * Handles a response (cache line fill/write ack) from the bus.
170 * @param pkt The request being responded to.
171 */
172 void handleResponse(PacketPtr &pkt);
173
174 /**
175 * Selects a coherence message to forward to lower levels of the hierarchy.
176 * @return The coherence message to forward.
177 */
178 virtual PacketPtr getCoherencePacket();
179
180 /**
181 * Snoops bus transactions to maintain coherence.
182 * @param pkt The current bus transaction.
183 */
184 void snoop(PacketPtr &pkt);
185
186 void snoopResponse(PacketPtr &pkt);
187
188 /**
189 * Invalidates the block containing address if found.
190 * @param addr The address to look for.
191 * @param asid The address space ID of the address.
192 * @todo Is this function necessary?
193 */
194 void invalidateBlk(Addr addr);
195
196 /**
197 * Squash all requests associated with specified thread.
198 * intended for use by I-cache.
199 * @param threadNum The thread to squash.
200 */
201 void squash(int threadNum)
202 {
203 missQueue->squash(threadNum);
204 }
205
206 /**
207 * Return the number of outstanding misses in a Cache.
208 * Default returns 0.
209 *
210 * @retval unsigned The number of missing still outstanding.
211 */
212 unsigned outstandingMisses() const
213 {
214 return missQueue->getMisses();
215 }
216
217 /**
218 * Perform the access specified in the request and return the estimated
219 * time of completion. This function can either update the hierarchy state
220 * or just perform the access wherever the data is found depending on the
221 * state of the update flag.
222 * @param pkt The memory request to satisfy
223 * @param update If true, update the hierarchy, otherwise just perform the
224 * request.
225 * @return The estimated completion time.
226 */
227 Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
228
229 /**
230 * Snoop for the provided request in the cache and return the estimated
231 * time of completion.
232 * @todo Can a snoop probe not change state?
233 * @param pkt The memory request to satisfy
234 * @param update If true, update the hierarchy, otherwise just perform the
235 * request.
236 * @return The estimated completion time.
237 */
238 Tick snoopProbe(PacketPtr &pkt);
239};
240
241#endif // __CACHE_HH__
| 119 bool prefetch_access, int hit_latency)
120 : tags(_tags), missQueue(mq), coherence(coh),
121 baseParams(params),
122 prefetcher(_prefetcher), prefetchAccess(prefetch_access),
123 hitLatency(hit_latency)
124 {
125 }
126 };
127
128 /** Instantiates a basic cache object. */
129 Cache(const std::string &_name, Params ¶ms);
130
131 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
132 bool isCpuSide);
133
134 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
135
136 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
137
138 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
139
140 void regStats();
141
142 /**
143 * Performs the access specified by the request.
144 * @param pkt The request to perform.
145 * @return The result of the access.
146 */
147 bool access(PacketPtr &pkt);
148
149 /**
150 * Selects a request to send on the bus.
151 * @return The memory request to service.
152 */
153 virtual PacketPtr getPacket();
154
155 /**
156 * Was the request was sent successfully?
157 * @param pkt The request.
158 * @param success True if the request was sent successfully.
159 */
160 virtual void sendResult(PacketPtr &pkt, MSHR* mshr, bool success);
161
162 /**
163 * Was the CSHR request was sent successfully?
164 * @param pkt The request.
165 * @param success True if the request was sent successfully.
166 */
167 virtual void sendCoherenceResult(PacketPtr &pkt, MSHR* cshr, bool success);
168
169 /**
170 * Handles a response (cache line fill/write ack) from the bus.
171 * @param pkt The request being responded to.
172 */
173 void handleResponse(PacketPtr &pkt);
174
175 /**
176 * Selects a coherence message to forward to lower levels of the hierarchy.
177 * @return The coherence message to forward.
178 */
179 virtual PacketPtr getCoherencePacket();
180
181 /**
182 * Snoops bus transactions to maintain coherence.
183 * @param pkt The current bus transaction.
184 */
185 void snoop(PacketPtr &pkt);
186
187 void snoopResponse(PacketPtr &pkt);
188
189 /**
190 * Invalidates the block containing address if found.
191 * @param addr The address to look for.
192 * @param asid The address space ID of the address.
193 * @todo Is this function necessary?
194 */
195 void invalidateBlk(Addr addr);
196
197 /**
198 * Squash all requests associated with specified thread.
199 * intended for use by I-cache.
200 * @param threadNum The thread to squash.
201 */
202 void squash(int threadNum)
203 {
204 missQueue->squash(threadNum);
205 }
206
207 /**
208 * Return the number of outstanding misses in a Cache.
209 * Default returns 0.
210 *
211 * @retval unsigned The number of missing still outstanding.
212 */
213 unsigned outstandingMisses() const
214 {
215 return missQueue->getMisses();
216 }
217
218 /**
219 * Perform the access specified in the request and return the estimated
220 * time of completion. This function can either update the hierarchy state
221 * or just perform the access wherever the data is found depending on the
222 * state of the update flag.
223 * @param pkt The memory request to satisfy
224 * @param update If true, update the hierarchy, otherwise just perform the
225 * request.
226 * @return The estimated completion time.
227 */
228 Tick probe(PacketPtr &pkt, bool update, CachePort * otherSidePort);
229
230 /**
231 * Snoop for the provided request in the cache and return the estimated
232 * time of completion.
233 * @todo Can a snoop probe not change state?
234 * @param pkt The memory request to satisfy
235 * @param update If true, update the hierarchy, otherwise just perform the
236 * request.
237 * @return The estimated completion time.
238 */
239 Tick snoopProbe(PacketPtr &pkt);
240};
241
242#endif // __CACHE_HH__
|