1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47// forward declarations
48class Bus;
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Dave Greene
30 * Steve Reinhardt
31 */
32
33/**
34 * @file
35 * Describes a cache based on template policies.
36 */
37
38#ifndef __CACHE_HH__
39#define __CACHE_HH__
40
41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47// forward declarations
48class Bus;
|
49class ExecContext;
| |
50
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */
58template <class TagStore, class Buffering, class Coherence>
59class Cache : public BaseCache
60{
61 public:
62 /** Define the type of cache block to use. */
63 typedef typename TagStore::BlkType BlkType;
64
65 bool prefetchAccess;
66 protected:
67
68 /** Tag and data Storage */
69 TagStore *tags;
70 /** Miss and Writeback handler */
71 Buffering *missQueue;
72 /** Coherence protocol. */
73 Coherence *coherence;
74
75 /** Prefetcher */
76 Prefetcher<TagStore, Buffering> *prefetcher;
77
78 /** Do fast copies in this cache. */
79 bool doCopy;
80
81 /** Block on a delayed copy. */
82 bool blockOnCopy;
83
84 /**
85 * The clock ratio of the outgoing bus.
86 * Used for calculating critical word first.
87 */
88 int busRatio;
89
90 /**
91 * The bus width in bytes of the outgoing bus.
92 * Used for calculating critical word first.
93 */
94 int busWidth;
95
96 /**
97 * A permanent mem req to always be used to cause invalidations.
98 * Used to append to target list, to cause an invalidation.
99 */
100 Packet * invalidatePkt;
101
102 /**
103 * Temporarily move a block into a MSHR.
104 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
105 */
106 void pseudoFill(Addr addr, int asid);
107
108 /**
109 * Temporarily move a block into an existing MSHR.
110 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
111 */
112 void pseudoFill(MSHR *mshr);
113
114 public:
115
116 class Params
117 {
118 public:
119 TagStore *tags;
120 Buffering *missQueue;
121 Coherence *coherence;
122 bool doCopy;
123 bool blockOnCopy;
124 BaseCache::Params baseParams;
125 Bus *in;
126 Bus *out;
127 Prefetcher<TagStore, Buffering> *prefetcher;
128 bool prefetchAccess;
129
130 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
131 bool do_copy, BaseCache::Params params, Bus * in_bus,
132 Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
133 bool prefetch_access)
134 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
135 blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
136 prefetcher(_prefetcher), prefetchAccess(prefetch_access)
137 {
138 }
139 };
140
141 /** Instantiates a basic cache object. */
142 Cache(const std::string &_name, HierParams *hier_params, Params ¶ms);
143
144 void regStats();
145
146 /**
147 * Performs the access specified by the request.
148 * @param req The request to perform.
149 * @return The result of the access.
150 */
151 MemAccessResult access(Packet * &pkt);
152
153 /**
154 * Selects a request to send on the bus.
155 * @return The memory request to service.
156 */
157 Packet * getPacket();
158
159 /**
160 * Was the request was sent successfully?
161 * @param req The request.
162 * @param success True if the request was sent successfully.
163 */
164 void sendResult(Packet * &pkt, bool success);
165
166 /**
167 * Handles a response (cache line fill/write ack) from the bus.
168 * @param req The request being responded to.
169 */
170 void handleResponse(Packet * &pkt);
171
172 /**
173 * Start handling a copy transaction.
174 * @param req The copy request to perform.
175 */
176 void startCopy(Packet * &pkt);
177
178 /**
179 * Handle a delayed copy transaction.
180 * @param req The delayed copy request to continue.
181 * @param addr The address being responded to.
182 * @param blk The block of the current response.
183 * @param mshr The mshr being handled.
184 */
185 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
186
187 /**
188 * Selects a coherence message to forward to lower levels of the hierarchy.
189 * @return The coherence message to forward.
190 */
191 Packet * getCoherenceReq();
192
193 /**
194 * Snoops bus transactions to maintain coherence.
195 * @param req The current bus transaction.
196 */
197 void snoop(Packet * &pkt);
198
199 void snoopResponse(Packet * &pkt);
200
201 /**
202 * Invalidates the block containing address if found.
203 * @param addr The address to look for.
204 * @param asid The address space ID of the address.
205 * @todo Is this function necessary?
206 */
207 void invalidateBlk(Addr addr, int asid);
208
209 /**
210 * Aquash all requests associated with specified thread.
211 * intended for use by I-cache.
| 49
50/**
51 * A template-policy based cache. The behavior of the cache can be altered by
52 * supplying different template policies. TagStore handles all tag and data
53 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
54 * @sa MissQueue. Coherence handles all coherence policy details @sa
55 * UniCoherence, SimpleMultiCoherence.
56 */
57template <class TagStore, class Buffering, class Coherence>
58class Cache : public BaseCache
59{
60 public:
61 /** Define the type of cache block to use. */
62 typedef typename TagStore::BlkType BlkType;
63
64 bool prefetchAccess;
65 protected:
66
67 /** Tag and data Storage */
68 TagStore *tags;
69 /** Miss and Writeback handler */
70 Buffering *missQueue;
71 /** Coherence protocol. */
72 Coherence *coherence;
73
74 /** Prefetcher */
75 Prefetcher<TagStore, Buffering> *prefetcher;
76
77 /** Do fast copies in this cache. */
78 bool doCopy;
79
80 /** Block on a delayed copy. */
81 bool blockOnCopy;
82
83 /**
84 * The clock ratio of the outgoing bus.
85 * Used for calculating critical word first.
86 */
87 int busRatio;
88
89 /**
90 * The bus width in bytes of the outgoing bus.
91 * Used for calculating critical word first.
92 */
93 int busWidth;
94
95 /**
96 * A permanent mem req to always be used to cause invalidations.
97 * Used to append to target list, to cause an invalidation.
98 */
99 Packet * invalidatePkt;
100
101 /**
102 * Temporarily move a block into a MSHR.
103 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
104 */
105 void pseudoFill(Addr addr, int asid);
106
107 /**
108 * Temporarily move a block into an existing MSHR.
109 * @todo Remove this when LSQ/SB are fixed and implemented in memtest.
110 */
111 void pseudoFill(MSHR *mshr);
112
113 public:
114
115 class Params
116 {
117 public:
118 TagStore *tags;
119 Buffering *missQueue;
120 Coherence *coherence;
121 bool doCopy;
122 bool blockOnCopy;
123 BaseCache::Params baseParams;
124 Bus *in;
125 Bus *out;
126 Prefetcher<TagStore, Buffering> *prefetcher;
127 bool prefetchAccess;
128
129 Params(TagStore *_tags, Buffering *mq, Coherence *coh,
130 bool do_copy, BaseCache::Params params, Bus * in_bus,
131 Bus * out_bus, Prefetcher<TagStore, Buffering> *_prefetcher,
132 bool prefetch_access)
133 : tags(_tags), missQueue(mq), coherence(coh), doCopy(do_copy),
134 blockOnCopy(false), baseParams(params), in(in_bus), out(out_bus),
135 prefetcher(_prefetcher), prefetchAccess(prefetch_access)
136 {
137 }
138 };
139
140 /** Instantiates a basic cache object. */
141 Cache(const std::string &_name, HierParams *hier_params, Params ¶ms);
142
143 void regStats();
144
145 /**
146 * Performs the access specified by the request.
147 * @param req The request to perform.
148 * @return The result of the access.
149 */
150 MemAccessResult access(Packet * &pkt);
151
152 /**
153 * Selects a request to send on the bus.
154 * @return The memory request to service.
155 */
156 Packet * getPacket();
157
158 /**
159 * Was the request was sent successfully?
160 * @param req The request.
161 * @param success True if the request was sent successfully.
162 */
163 void sendResult(Packet * &pkt, bool success);
164
165 /**
166 * Handles a response (cache line fill/write ack) from the bus.
167 * @param req The request being responded to.
168 */
169 void handleResponse(Packet * &pkt);
170
171 /**
172 * Start handling a copy transaction.
173 * @param req The copy request to perform.
174 */
175 void startCopy(Packet * &pkt);
176
177 /**
178 * Handle a delayed copy transaction.
179 * @param req The delayed copy request to continue.
180 * @param addr The address being responded to.
181 * @param blk The block of the current response.
182 * @param mshr The mshr being handled.
183 */
184 void handleCopy(Packet * &pkt, Addr addr, BlkType *blk, MSHR *mshr);
185
186 /**
187 * Selects a coherence message to forward to lower levels of the hierarchy.
188 * @return The coherence message to forward.
189 */
190 Packet * getCoherenceReq();
191
192 /**
193 * Snoops bus transactions to maintain coherence.
194 * @param req The current bus transaction.
195 */
196 void snoop(Packet * &pkt);
197
198 void snoopResponse(Packet * &pkt);
199
200 /**
201 * Invalidates the block containing address if found.
202 * @param addr The address to look for.
203 * @param asid The address space ID of the address.
204 * @todo Is this function necessary?
205 */
206 void invalidateBlk(Addr addr, int asid);
207
208 /**
209 * Aquash all requests associated with specified thread.
210 * intended for use by I-cache.
|
212 * @param thread_number The thread to squash.
| 211 * @param req->getThreadNum()ber The thread to squash.
|
213 */
| 212 */
|
214 void squash(int thread_number)
| 213 void squash(int threadNum)
|
215 {
| 214 {
|
216 missQueue->squash(thread_number);
| 215 missQueue->squash(threadNum);
|
217 }
218
219 /**
220 * Return the number of outstanding misses in a Cache.
221 * Default returns 0.
222 *
223 * @retval unsigned The number of missing still outstanding.
224 */
225 unsigned outstandingMisses() const
226 {
227 return missQueue->getMisses();
228 }
229
230 /**
231 * Send a response to the slave interface.
232 * @param req The request being responded to.
233 * @param time The time the response is ready.
234 */
235 void respond(Packet * &pkt, Tick time)
236 {
237 si->respond(pkt,time);
238 }
239
240 /**
241 * Perform the access specified in the request and return the estimated
242 * time of completion. This function can either update the hierarchy state
243 * or just perform the access wherever the data is found depending on the
244 * state of the update flag.
245 * @param req The memory request to satisfy
246 * @param update If true, update the hierarchy, otherwise just perform the
247 * request.
248 * @return The estimated completion time.
249 */
250 Tick probe(Packet * &pkt, bool update);
251
252 /**
253 * Snoop for the provided request in the cache and return the estimated
254 * time of completion.
255 * @todo Can a snoop probe not change state?
256 * @param req The memory request to satisfy
257 * @param update If true, update the hierarchy, otherwise just perform the
258 * request.
259 * @return The estimated completion time.
260 */
261 Tick snoopProbe(Packet * &pkt, bool update);
262};
263
264#endif // __CACHE_HH__
| 216 }
217
218 /**
219 * Return the number of outstanding misses in a Cache.
220 * Default returns 0.
221 *
222 * @retval unsigned The number of missing still outstanding.
223 */
224 unsigned outstandingMisses() const
225 {
226 return missQueue->getMisses();
227 }
228
229 /**
230 * Send a response to the slave interface.
231 * @param req The request being responded to.
232 * @param time The time the response is ready.
233 */
234 void respond(Packet * &pkt, Tick time)
235 {
236 si->respond(pkt,time);
237 }
238
239 /**
240 * Perform the access specified in the request and return the estimated
241 * time of completion. This function can either update the hierarchy state
242 * or just perform the access wherever the data is found depending on the
243 * state of the update flag.
244 * @param req The memory request to satisfy
245 * @param update If true, update the hierarchy, otherwise just perform the
246 * request.
247 * @return The estimated completion time.
248 */
249 Tick probe(Packet * &pkt, bool update);
250
251 /**
252 * Snoop for the provided request in the cache and return the estimated
253 * time of completion.
254 * @todo Can a snoop probe not change state?
255 * @param req The memory request to satisfy
256 * @param update If true, update the hierarchy, otherwise just perform the
257 * request.
258 * @return The estimated completion time.
259 */
260 Tick snoopProbe(Packet * &pkt, bool update);
261};
262
263#endif // __CACHE_HH__
|