cache.hh (4671:5d29d3be0f79) | cache.hh (4672:cc97e595e07d) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34/** 35 * @file 36 * Describes a cache based on template policies. 37 */ 38 39#ifndef __CACHE_HH__ 40#define __CACHE_HH__ 41 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 25 unchanged lines hidden (view full) --- 34/** 35 * @file 36 * Describes a cache based on template policies. 37 */ 38 39#ifndef __CACHE_HH__ 40#define __CACHE_HH__ 41 |
42#include "base/compression/base.hh" | |
43#include "base/misc.hh" // fatal, panic, and warn | 42#include "base/misc.hh" // fatal, panic, and warn |
44#include "cpu/smt.hh" // SMT_MAX_THREADS | |
45 46#include "mem/cache/base_cache.hh" 47#include "mem/cache/cache_blk.hh" 48#include "mem/cache/miss/mshr.hh" 49 50#include "sim/eventq.hh" 51 52//Forward decleration 53class BasePrefetcher; 54 55/** 56 * A template-policy based cache. The behavior of the cache can be altered by 57 * supplying different template policies. TagStore handles all tag and data | 43 44#include "mem/cache/base_cache.hh" 45#include "mem/cache/cache_blk.hh" 46#include "mem/cache/miss/mshr.hh" 47 48#include "sim/eventq.hh" 49 50//Forward decleration 51class BasePrefetcher; 52 53/** 54 * A template-policy based cache. The behavior of the cache can be altered by 55 * supplying different template policies. TagStore handles all tag and data |
58 * storage @sa TagStore. Buffering handles all misses and writes/writebacks 59 * @sa MissQueue. Coherence handles all coherence policy details @sa 60 * UniCoherence, SimpleMultiCoherence. | 56 * storage @sa TagStore. |
61 */ | 57 */ |
62template <class TagStore, class Coherence> | 58template |
63class Cache : public BaseCache 64{ 65 public: 66 /** Define the type of cache block to use. */ 67 typedef typename TagStore::BlkType BlkType; 68 /** A typedef for a list of BlkType pointers. */ 69 typedef typename TagStore::BlkList BlkList; 70 71 bool prefetchAccess; 72 73 protected: 74 75 class CpuSidePort : public CachePort 76 { 77 public: 78 CpuSidePort(const std::string &_name, | 59class Cache : public BaseCache 60{ 61 public: 62 /** Define the type of cache block to use. */ 63 typedef typename TagStore::BlkType BlkType; 64 /** A typedef for a list of BlkType pointers. */ 65 typedef typename TagStore::BlkList BlkList; 66 67 bool prefetchAccess; 68 69 protected: 70 71 class CpuSidePort : public CachePort 72 { 73 public: 74 CpuSidePort(const std::string &_name, |
79 Cache<TagStore,Coherence> *_cache); | 75 Cache |
80 81 // BaseCache::CachePort just has a BaseCache *; this function 82 // lets us get back the type info we lost when we stored the 83 // cache pointer there. | 76 77 // BaseCache::CachePort just has a BaseCache *; this function 78 // lets us get back the type info we lost when we stored the 79 // cache pointer there. |
84 Cache<TagStore,Coherence> *myCache() { 85 return static_cast<Cache<TagStore,Coherence> *>(cache); | 80 Cache 81 return static_cast |
86 } 87 88 virtual void getDeviceAddressRanges(AddrRangeList &resp, 89 bool &snoop); 90 91 virtual bool recvTiming(PacketPtr pkt); 92 93 virtual Tick recvAtomic(PacketPtr pkt); 94 95 virtual void recvFunctional(PacketPtr pkt); 96 }; 97 98 class MemSidePort : public CachePort 99 { 100 public: 101 MemSidePort(const std::string &_name, | 82 } 83 84 virtual void getDeviceAddressRanges(AddrRangeList &resp, 85 bool &snoop); 86 87 virtual bool recvTiming(PacketPtr pkt); 88 89 virtual Tick recvAtomic(PacketPtr pkt); 90 91 virtual void recvFunctional(PacketPtr pkt); 92 }; 93 94 class MemSidePort : public CachePort 95 { 96 public: 97 MemSidePort(const std::string &_name, |
102 Cache<TagStore,Coherence> *_cache); | 98 Cache |
103 104 // BaseCache::CachePort just has a BaseCache *; this function 105 // lets us get back the type info we lost when we stored the 106 // cache pointer there. | 99 100 // BaseCache::CachePort just has a BaseCache *; this function 101 // lets us get back the type info we lost when we stored the 102 // cache pointer there. |
107 Cache<TagStore,Coherence> *myCache() { 108 return static_cast<Cache<TagStore,Coherence> *>(cache); | 103 Cache 104 return static_cast |
109 } 110 111 void sendPacket(); 112 113 void processSendEvent(); 114 115 virtual void getDeviceAddressRanges(AddrRangeList &resp, 116 bool &snoop); --- 8 unchanged lines hidden (view full) --- 125 126 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 127 SendEvent; 128 }; 129 130 /** Tag and data Storage */ 131 TagStore *tags; 132 | 105 } 106 107 void sendPacket(); 108 109 void processSendEvent(); 110 111 virtual void getDeviceAddressRanges(AddrRangeList &resp, 112 bool &snoop); --- 8 unchanged lines hidden (view full) --- 121 122 typedef EventWrapper<MemSidePort, &MemSidePort::processSendEvent> 123 SendEvent; 124 }; 125 126 /** Tag and data Storage */ 127 TagStore *tags; 128 |
133 /** Coherence protocol. */ 134 Coherence *coherence; 135 | |
136 /** Prefetcher */ 137 BasePrefetcher *prefetcher; 138 139 /** Temporary cache block for occasional transitory use */ 140 BlkType *tempBlock; 141 142 /** 143 * Can this cache should allocate a block on a line-sized write miss. --- 63 unchanged lines hidden (view full) --- 207 PacketPtr writebackBlk(BlkType *blk); 208 209 public: 210 211 class Params 212 { 213 public: 214 TagStore *tags; | 129 /** Prefetcher */ 130 BasePrefetcher *prefetcher; 131 132 /** Temporary cache block for occasional transitory use */ 133 BlkType *tempBlock; 134 135 /** 136 * Can this cache should allocate a block on a line-sized write miss. --- 63 unchanged lines hidden (view full) --- 200 PacketPtr writebackBlk(BlkType *blk); 201 202 public: 203 204 class Params 205 { 206 public: 207 TagStore *tags; |
215 Coherence *coherence; | |
216 BaseCache::Params baseParams; 217 BasePrefetcher*prefetcher; 218 bool prefetchAccess; 219 const bool doFastWrites; 220 const bool prefetchMiss; 221 | 208 BaseCache::Params baseParams; 209 BasePrefetcher*prefetcher; 210 bool prefetchAccess; 211 const bool doFastWrites; 212 const bool prefetchMiss; 213 |
222 Params(TagStore *_tags, Coherence *coh, | 214 Params(TagStore *_tags, |
223 BaseCache::Params params, 224 BasePrefetcher *_prefetcher, 225 bool prefetch_access, int hit_latency, 226 bool do_fast_writes, 227 bool prefetch_miss) | 215 BaseCache::Params params, 216 BasePrefetcher *_prefetcher, 217 bool prefetch_access, int hit_latency, 218 bool do_fast_writes, 219 bool prefetch_miss) |
228 : tags(_tags), coherence(coh), | 220 : tags(_tags), |
229 baseParams(params), 230 prefetcher(_prefetcher), prefetchAccess(prefetch_access), 231 doFastWrites(do_fast_writes), 232 prefetchMiss(prefetch_miss) 233 { 234 } 235 }; 236 --- 101 unchanged lines hidden --- | 221 baseParams(params), 222 prefetcher(_prefetcher), prefetchAccess(prefetch_access), 223 doFastWrites(do_fast_writes), 224 prefetchMiss(prefetch_miss) 225 { 226 } 227 }; 228 --- 101 unchanged lines hidden --- |