1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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132
133 /** Coherence protocol. */
134 Coherence *coherence;
135
136 /** Prefetcher */
137 BasePrefetcher *prefetcher;
138
139 /**
140 * The clock ratio of the outgoing bus.
141 * Used for calculating critical word first.
142 */
143 int busRatio;
144
145 /**
146 * The bus width in bytes of the outgoing bus.
147 * Used for calculating critical word first.
148 */
149 int busWidth;
150
151 /**
152 * The latency of a hit in this device.
153 */
154 int hitLatency;
155
156 /**
157 * Can this cache should allocate a block on a line-sized write miss.
158 */
159 const bool doFastWrites;
160
161 const bool prefetchMiss;
162
163 /**
164 * Handle a replacement for the given request.

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299 /**
300 * Squash all requests associated with specified thread.
301 * intended for use by I-cache.
302 * @param threadNum The thread to squash.
303 */
304 void squash(int threadNum);
305
306 /**
307 * Allocate a new MSHR or write buffer to handle a miss.
308 * @param pkt The access that missed.
309 * @param time The time to continue processing the miss.
310 * @param isFill Whether to fetch & allocate a block
311 * or just forward the request.
312 */
313 MSHR *allocateBuffer(PacketPtr pkt, Tick time, bool requestBus);
314
315 /**
316 * Selects a outstanding request to service.
317 * @return The request to service, NULL if none found.
318 */
319 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
320 bool needsExclusive);
321 MSHR *getNextMSHR();
322 PacketPtr getTimingPacket();
323

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