1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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59template <class TagStore, class Coherence>
60class Cache : public BaseCache
61{
62 public:
63 /** Define the type of cache block to use. */
64 typedef typename TagStore::BlkType BlkType;
65
66 bool prefetchAccess;
67 protected:
68
69 /** Tag and data Storage */
70 TagStore *tags;
71 /** Miss and Writeback handler */
72 MissBuffer *missQueue;
73 /** Coherence protocol. */
74 Coherence *coherence;
75
76 /** Prefetcher */

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123 hitLatency(hit_latency)
124 {
125 }
126 };
127
128 /** Instantiates a basic cache object. */
129 Cache(const std::string &_name, Params &params);
130
131 virtual bool doTimingAccess(PacketPtr pkt, CachePort *cachePort,
132 bool isCpuSide);
133
134 virtual Tick doAtomicAccess(PacketPtr pkt, bool isCpuSide);
135
136 virtual void doFunctionalAccess(PacketPtr pkt, bool isCpuSide);
137
138 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
139
140 void regStats();
141
142 /**
143 * Performs the access specified by the request.
144 * @param pkt The request to perform.
145 * @return The result of the access.

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