1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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41#include "base/misc.hh" // fatal, panic, and warn
42#include "cpu/smt.hh" // SMT_MAX_THREADS
43
44#include "mem/cache/base_cache.hh"
45#include "mem/cache/prefetch/prefetcher.hh"
46
47// forward declarations
48class Bus;
49class ExecContext;
50
51/**
52 * A template-policy based cache. The behavior of the cache can be altered by
53 * supplying different template policies. TagStore handles all tag and data
54 * storage @sa TagStore. Buffering handles all misses and writes/writebacks
55 * @sa MissQueue. Coherence handles all coherence policy details @sa
56 * UniCoherence, SimpleMultiCoherence.
57 */

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204 * @param asid The address space ID of the address.
205 * @todo Is this function necessary?
206 */
207 void invalidateBlk(Addr addr, int asid);
208
209 /**
210 * Aquash all requests associated with specified thread.
211 * intended for use by I-cache.
212 * @param thread_number The thread to squash.
213 */
214 void squash(int thread_number)
215 {
216 missQueue->squash(thread_number);
217 }
218
219 /**
220 * Return the number of outstanding misses in a Cache.
221 * Default returns 0.
222 *
223 * @retval unsigned The number of missing still outstanding.
224 */

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