1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 73 unchanged lines hidden (view full) ---

82 std::unordered_set<RequestPtr> outstandingSnoop;
83
84 protected:
85 /**
86 * Turn line-sized writes into WriteInvalidate transactions.
87 */
88 void promoteWholeLineWrites(PacketPtr pkt);
89
90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat) override;
91
92 void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
93 Tick request_time) override;
94
95 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
96 Tick forward_time,
97 Tick request_time) override;
98
99 void recvTimingReq(PacketPtr pkt) override;
100
101 void doWritebacks(PacketPtr pkt, Tick forward_time) override;
102
103 void doWritebacksAtomic(PacketPtr pkt) override;
104
105 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
106 CacheBlk *blk) override;
107
108 void recvTimingSnoopReq(PacketPtr pkt) override;
109
110 void recvTimingSnoopResp(PacketPtr pkt) override;
111
112 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk) override;
113
114 Tick recvAtomic(PacketPtr pkt) override;
115
116 Tick recvAtomicSnoop(PacketPtr pkt) override;
117
118 void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
119 bool deferred_response = false,
120 bool pending_downgrade = false) override;

--- 55 unchanged lines hidden ---