1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
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342 return clusivity == Enums::mostly_incl ||
343 cmd == MemCmd::WriteLineReq ||
344 cmd == MemCmd::ReadReq ||
345 cmd == MemCmd::WriteReq ||
346 cmd.isPrefetch() ||
347 cmd.isLLSC();
348 }
349
350 /**
351 * Performs the access specified by the request.
352 * @param pkt The request to perform.
353 */
354 void recvTimingReq(PacketPtr pkt);
355
356 /**
357 * Insert writebacks into the write buffer
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2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
--- 333 unchanged lines hidden (view full) ---
342 return clusivity == Enums::mostly_incl ||
343 cmd == MemCmd::WriteLineReq ||
344 cmd == MemCmd::ReadReq ||
345 cmd == MemCmd::WriteReq ||
346 cmd.isPrefetch() ||
347 cmd.isLLSC();
348 }
349
350 /**
351 * Performs the access specified by the request.
352 * @param pkt The request to perform.
353 */
354 void recvTimingReq(PacketPtr pkt);
355
356 /**
357 * Insert writebacks into the write buffer
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