1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
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48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __MEM_CACHE_CACHE_HH__
53#define __MEM_CACHE_CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "mem/cache/tags/base.hh"
60#include "params/Cache.hh"
61#include "sim/eventq.hh"
62
63//Forward decleration
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189 */
190 void promoteWholeLineWrites(PacketPtr pkt);
191
192 /**
193 * Notify the prefetcher on every access, not just misses.
194 */
195 const bool prefetchOnAccess;
196
197 /**
198 * Upstream caches need this packet until true is returned, so
199 * hold it for deletion until a subsequent call
200 */
201 std::unique_ptr<Packet> pendingDelete;
202
203 /**
204 * Does all the processing necessary to perform the provided request.
205 * @param pkt The memory request to perform.
206 * @param blk The cache block to be updated.
207 * @param lat The latency of the access.
208 * @param writebacks List for any writebacks that need to be performed.
209 * @return Boolean indicating whether the request was satisfied.
210 */
211 bool access(PacketPtr pkt, CacheBlk *&blk,
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221 * given security space, assuming that the block is not currently
222 * in the cache. Append writebacks if any to provided packet
223 * list. Return free block frame. May return NULL if there are
224 * no replaceable blocks at the moment.
225 */
226 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
227
228 /**
229 * Populates a cache block and handles all outstanding requests for the
230 * satisfied fill request. This version takes two memory requests. One
231 * contains the fill data, the other is an optional target to satisfy.
232 * @param pkt The memory request with the fill data.
233 * @param blk The cache block if it already exists.
234 * @param writebacks List for any writebacks that need to be performed.
235 * @return Pointer to the new cache block.
236 */
237 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
238 PacketList &writebacks);
239
240
241 /**
242 * Performs the access specified by the request.
243 * @param pkt The request to perform.
244 * @return The result of the access.
245 */
246 bool recvTimingReq(PacketPtr pkt);
247
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2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
--- 37 unchanged lines hidden (view full) ---
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __MEM_CACHE_CACHE_HH__
53#define __MEM_CACHE_CACHE_HH__
54
55#include "base/misc.hh" // fatal, panic, and warn
56#include "mem/cache/base.hh"
57#include "mem/cache/blk.hh"
58#include "mem/cache/mshr.hh"
59#include "mem/cache/tags/base.hh"
60#include "params/Cache.hh"
61#include "sim/eventq.hh"
62
63//Forward decleration
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189 */
190 void promoteWholeLineWrites(PacketPtr pkt);
191
192 /**
193 * Notify the prefetcher on every access, not just misses.
194 */
195 const bool prefetchOnAccess;
196
197 /**
198 * Upstream caches need this packet until true is returned, so
199 * hold it for deletion until a subsequent call
200 */
201 std::unique_ptr<Packet> pendingDelete;
202
203 /**
204 * Does all the processing necessary to perform the provided request.
205 * @param pkt The memory request to perform.
206 * @param blk The cache block to be updated.
207 * @param lat The latency of the access.
208 * @param writebacks List for any writebacks that need to be performed.
209 * @return Boolean indicating whether the request was satisfied.
210 */
211 bool access(PacketPtr pkt, CacheBlk *&blk,
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221 * given security space, assuming that the block is not currently
222 * in the cache. Append writebacks if any to provided packet
223 * list. Return free block frame. May return NULL if there are
224 * no replaceable blocks at the moment.
225 */
226 CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
227
228 /**
229 * Populates a cache block and handles all outstanding requests for the
230 * satisfied fill request. This version takes two memory requests. One
231 * contains the fill data, the other is an optional target to satisfy.
232 * @param pkt The memory request with the fill data.
233 * @param blk The cache block if it already exists.
234 * @param writebacks List for any writebacks that need to be performed.
235 * @return Pointer to the new cache block.
236 */
237 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
238 PacketList &writebacks);
239
240
241 /**
242 * Performs the access specified by the request.
243 * @param pkt The request to perform.
244 * @return The result of the access.
245 */
246 bool recvTimingReq(PacketPtr pkt);
247
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