1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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247 bool recvTimingReq(PacketPtr pkt);
248
249 /**
250 * Insert writebacks into the write buffer
251 */
252 void doWritebacks(PacketList& writebacks, Tick forward_time);
253
254 /**
255 * Handles a response (cache line fill/write ack) from the bus.
256 * @param pkt The response packet
257 */
258 void recvTimingResp(PacketPtr pkt);
259
260 /**
261 * Snoops bus transactions to maintain coherence.
262 * @param pkt The current bus transaction.

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370 * prioritizing among those sources on the fly.
371 */
372 MSHR *getNextMSHR();
373
374 /**
375 * Send up a snoop request and find cached copies. If cached copies are
376 * found, set the BLOCK_CACHED flag in pkt.
377 */
378 bool isCachedAbove(const PacketPtr pkt) const;
379
380 /**
381 * Selects an outstanding request to service. Called when the
382 * cache gets granted the downstream bus in timing mode.
383 * @return The request to service, NULL if none found.
384 */
385 PacketPtr getTimingPacket();
386

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