1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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285 * @note This shouldn't normally happen, but we need to handle it
286 * since some architecture models don't implement cache
287 * maintenance operations. We won't even try to get a decent
288 * timing here since the line should have been flushed earlier by
289 * a cache maintenance operation.
290 */
291 void uncacheableFlush(PacketPtr pkt);
292
293 /**
294 * Performs the access specified by the request.
295 * @param pkt The request to perform.
296 * @return The result of the access.
297 */
298 bool timingAccess(PacketPtr pkt);
299
300 /**

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345 * @param blk The block currently in the cache corresponding to
346 * cpu_pkt (NULL if none).
347 * @param needsExclusive Indicates that an exclusive copy is required
348 * even if the request in cpu_pkt doesn't indicate that.
349 * @return A new Packet containing the request, or NULL if the
350 * current request in cpu_pkt should just be forwarded on.
351 */
352 PacketPtr getBusPacket(PacketPtr cpu_pkt, BlkType *blk,
353 bool needsExclusive) const;
354
355 /**
356 * Return the next MSHR to service, either a pending miss from the
357 * mshrQueue, a buffered write from the write buffer, or something
358 * from the prefetcher. This function is responsible for
359 * prioritizing among those sources on the fly.
360 */
361 MSHR *getNextMSHR();

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378 /**
379 * Return whether there are any outstanding misses.
380 */
381 bool outstandingMisses() const
382 {
383 return mshrQueue.allocated != 0;
384 }
385
386 CacheBlk *findBlock(Addr addr) const {
387 return tags->findBlock(addr);
388 }
389
390 bool inCache(Addr addr) const {
391 return (tags->findBlock(addr) != 0);
392 }
393
394 bool inMissQueue(Addr addr) const {
395 return (mshrQueue.findMatch(addr) != 0);
396 }
397
398 /**
399 * Find next request ready time from among possible sources.
400 */
401 Tick nextMSHRReadyTime() const;
402
403 public:
404 /** Instantiates a basic cache object. */
405 Cache(const Params *p, TagStore *tags);
406
407 void regStats();
408
409 /** serialize the state of the caches
410 * We currently don't support checkpointing cache state, so this panics.
411 */
412 virtual void serialize(std::ostream &os);
413 void unserialize(Checkpoint *cp, const std::string &section);
414};
415
416#endif // __CACHE_HH__