1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Dave Greene
42 * Steve Reinhardt
43 * Ron Dreslinski
44 * Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache based on template policies.
50 */
51
52#ifndef __CACHE_HH__

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72 public:
73 /** Define the type of cache block to use. */
74 typedef typename TagStore::BlkType BlkType;
75 /** A typedef for a list of BlkType pointers. */
76 typedef typename TagStore::BlkList BlkList;
77
78 protected:
79
80 /**
81 * The CPU-side port extends the base cache slave port with access
82 * functions for functional, atomic and timing requests.
83 */
84 class CpuSidePort : public CacheSlavePort
85 {
86 private:
87
88 // a pointer to our specific cache implementation
89 Cache<TagStore> *cache;
90
91 protected:
92
93 virtual bool recvTiming(PacketPtr pkt);
94
95 virtual Tick recvAtomic(PacketPtr pkt);
96
97 virtual void recvFunctional(PacketPtr pkt);
98
99 virtual unsigned deviceBlockSize() const
100 { return cache->getBlockSize(); }
101
102 virtual AddrRangeList getAddrRanges();
103
104 public:
105
106 CpuSidePort(const std::string &_name, Cache<TagStore> *_cache,
107 const std::string &_label);
108
109 };
110
111 /**
112 * The memory-side port extends the base cache master port with
113 * access functions for functional, atomic and timing snoops.
114 */
115 class MemSidePort : public CacheMasterPort
116 {
117 private:
118
119 // a pointer to our specific cache implementation
120 Cache<TagStore> *cache;
121
122 protected:
123
124 virtual bool recvTiming(PacketPtr pkt);
125
126 virtual Tick recvAtomic(PacketPtr pkt);
127
128 virtual void recvFunctional(PacketPtr pkt);
129
130 virtual unsigned deviceBlockSize() const
131 { return cache->getBlockSize(); }
132
133 public:
134
135 MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
136 const std::string &_label);
137
138 /**
139 * Overload sendDeferredPacket of SimpleTimingPort.
140 */
141 virtual void sendDeferredPacket();
142 };
143
144 /** Tag and data Storage */
145 TagStore *tags;
146
147 /** Prefetcher */
148 BasePrefetcher *prefetcher;
149

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