1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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144 };
145
146 /** Instantiates a basic cache object. */
147 Cache(const std::string &_name, Params &params);
148
149 virtual bool doTimingAccess(Packet *pkt, CachePort *cachePort,
150 bool isCpuSide);
151
152 virtual Tick doAtomicAccess(Packet *pkt, bool isCpuSide);
153
154 virtual void doFunctionalAccess(Packet *pkt, bool isCpuSide);
155
156 virtual void recvStatusChange(Port::Status status, bool isCpuSide);
157
158 void regStats();
159
160 /**
161 * Performs the access specified by the request.
162 * @param req The request to perform.

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