1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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82 std::unordered_set<RequestPtr> outstandingSnoop;
83
84 protected:
85 /**
86 * Turn line-sized writes into WriteInvalidate transactions.
87 */
88 void promoteWholeLineWrites(PacketPtr pkt);
89
90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
91 PacketList &writebacks) override;
92
93 void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
94 Tick request_time) override;
95
96 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
97 Tick forward_time,
98 Tick request_time) override;
99
100 void recvTimingReq(PacketPtr pkt) override;
101
102 void doWritebacks(PacketList& writebacks, Tick forward_time) override;
103
104 void doWritebacksAtomic(PacketList& writebacks) override;
105
106 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
107 CacheBlk *blk) override;
108
109 void recvTimingSnoopReq(PacketPtr pkt) override;
110
111 void recvTimingSnoopResp(PacketPtr pkt) override;
112
113 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk,
114 PacketList &writebacks) override;
115
116 Tick recvAtomic(PacketPtr pkt) override;
117
118 Tick recvAtomicSnoop(PacketPtr pkt) override;
119
120 void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
121 bool deferred_response = false,
122 bool pending_downgrade = false) override;

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