1/*
2 * Copyright (c) 2012-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41 * Dave Greene
42 * Steve Reinhardt
43 * Ron Dreslinski
44 * Andreas Hansson
45 */
46
47/**
48 * @file
49 * Describes a cache
50 */
51
52#ifndef __MEM_CACHE_CACHE_HH__
53#define __MEM_CACHE_CACHE_HH__
54
55#include <cstdint>
56#include <unordered_set>
57
58#include "base/types.hh"
59#include "mem/cache/base.hh"
60#include "mem/packet.hh"
61
62class CacheBlk;
63struct CacheParams;
64class MSHR;
65
66/**
67 * A coherent cache that can be arranged in flexible topologies.
68 */
69class Cache : public BaseCache
70{
71 protected:
72 /**
73 * This cache should allocate a block on a line-sized write miss.
74 */
75 const bool doFastWrites;
76
77 /**
78 * Store the outstanding requests that we are expecting snoop
79 * responses from so we can determine which snoop responses we
80 * generated and which ones were merely forwarded.
81 */
82 std::unordered_set<RequestPtr> outstandingSnoop;
83
84 protected:
85 /**
86 * Turn line-sized writes into WriteInvalidate transactions.
87 */
88 void promoteWholeLineWrites(PacketPtr pkt);
89
90 bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
91 PacketList &writebacks) override;
92
93 void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
94 Tick request_time) override;
95
96 void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
97 Tick forward_time,
98 Tick request_time) override;
99
100 void recvTimingReq(PacketPtr pkt) override;
101
102 void doWritebacks(PacketList& writebacks, Tick forward_time) override;
103
104 void doWritebacksAtomic(PacketList& writebacks) override;
105
106 void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
107 PacketList& writebacks) override;
108
109 void recvTimingSnoopReq(PacketPtr pkt) override;
110
111 void recvTimingSnoopResp(PacketPtr pkt) override;
112
113 Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
114 PacketList &writebacks) override;
115
116 Tick recvAtomic(PacketPtr pkt) override;
117
118 Tick recvAtomicSnoop(PacketPtr pkt) override;
119
120 void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
121 bool deferred_response = false,
122 bool pending_downgrade = false) override;
123
124 void doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
125 bool already_copied, bool pending_inval);
126
127 /**
128 * Perform an upward snoop if needed, and update the block state
129 * (possibly invalidating the block). Also create a response if required.
130 *
131 * @param pkt Snoop packet
132 * @param blk Cache block being snooped
133 * @param is_timing Timing or atomic for the response
134 * @param is_deferred Is this a deferred snoop or not?
135 * @param pending_inval Do we have a pending invalidation?
136 *
137 * @return The snoop delay incurred by the upwards snoop
138 */
139 uint32_t handleSnoop(PacketPtr pkt, CacheBlk *blk,
140 bool is_timing, bool is_deferred, bool pending_inval);
141
142 M5_NODISCARD PacketPtr evictBlock(CacheBlk *blk) override;
143
144 void evictBlock(CacheBlk *blk, PacketList &writebacks) override;
145
146 /**
147 * Create a CleanEvict request for the given block.
148 *
149 * @param blk The block to evict.
150 * @return The CleanEvict request for the block.
151 */
152 PacketPtr cleanEvictBlk(CacheBlk *blk);
153
154 PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
155 bool needsWritable) const override;
156
157 /**
158 * Send up a snoop request and find cached copies. If cached copies are
159 * found, set the BLOCK_CACHED flag in pkt.
160 */
161 bool isCachedAbove(PacketPtr pkt, bool is_timing = true);
162
163 public:
164 /** Instantiates a basic cache object. */
165 Cache(const CacheParams *p);
166
167 /**
168 * Take an MSHR, turn it into a suitable downstream packet, and
169 * send it out. This construct allows a queue entry to choose a suitable
170 * approach based on its type.
171 *
172 * @param mshr The MSHR to turn into a packet and send
173 * @return True if the port is waiting for a retry
174 */
175 bool sendMSHRQueuePacket(MSHR* mshr) override;
176};
177
178#endif // __MEM_CACHE_CACHE_HH__