| cache.cc (14035:60068a2d56e0) | cache.cc (14118:3d2ee7721eb0) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2019 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 696 unchanged lines hidden (view full) --- 705 case MSHR::Target::FromCPU: 706 Tick completion_time; 707 // Here we charge on completion_time the delay of the xbar if the 708 // packet comes from it, charged on headerDelay. 709 completion_time = pkt->headerDelay; 710 711 // Software prefetch handling for cache closest to core 712 if (tgt_pkt->cmd.isSWPrefetch()) { | 1/* 2 * Copyright (c) 2010-2019 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 696 unchanged lines hidden (view full) --- 705 case MSHR::Target::FromCPU: 706 Tick completion_time; 707 // Here we charge on completion_time the delay of the xbar if the 708 // packet comes from it, charged on headerDelay. 709 completion_time = pkt->headerDelay; 710 711 // Software prefetch handling for cache closest to core 712 if (tgt_pkt->cmd.isSWPrefetch()) { |
| 713 if (tgt_pkt->needsWritable()) { 714 // All other copies of the block were invalidated and we 715 // have an exclusive copy. 716 717 // The coherence protocol assumes that if we fetched an 718 // exclusive copy of the block, we have the intention to 719 // modify it. Therefore the MSHR for the PrefetchExReq has 720 // been the point of ordering and this cache has commited 721 // to respond to snoops for the block. 722 // 723 // In most cases this is true anyway - a PrefetchExReq 724 // will be followed by a WriteReq. However, if that 725 // doesn't happen, the block is not marked as dirty and 726 // the cache doesn't respond to snoops that has committed 727 // to do so. 728 // 729 // To avoid deadlocks in cases where there is a snoop 730 // between the PrefetchExReq and the expected WriteReq, we 731 // proactively mark the block as Dirty. 732 assert(blk); 733 blk->status |= BlkDirty; 734 735 panic_if(isReadOnly, "Prefetch exclusive requests from " 736 "read-only cache %s\n", name()); 737 } 738 |
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| 713 // a software prefetch would have already been ack'd 714 // immediately with dummy data so the core would be able to 715 // retire it. This request completes right here, so we 716 // deallocate it. 717 delete tgt_pkt; 718 break; // skip response 719 } 720 --- 681 unchanged lines hidden --- | 739 // a software prefetch would have already been ack'd 740 // immediately with dummy data so the core would be able to 741 // retire it. This request completes right here, so we 742 // deallocate it. 743 delete tgt_pkt; 744 break; // skip response 745 } 746 --- 681 unchanged lines hidden --- |