cache.cc (13948:f8666d4d5855) cache.cc (13954:2f400a5f2627)
1/*
2 * Copyright (c) 2010-2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 283 unchanged lines hidden (view full) ---

292 memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time);
293}
294
295void
296Cache::promoteWholeLineWrites(PacketPtr pkt)
297{
298 // Cache line clearing instructions
299 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
1/*
2 * Copyright (c) 2010-2019 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 283 unchanged lines hidden (view full) ---

292 memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time);
293}
294
295void
296Cache::promoteWholeLineWrites(PacketPtr pkt)
297{
298 // Cache line clearing instructions
299 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
300 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
300 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0) &&
301 !pkt->isMaskedWrite()) {
301 pkt->cmd = MemCmd::WriteLineReq;
302 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
303 }
304}
305
306void
307Cache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
308{

--- 1080 unchanged lines hidden --- 		302 pkt->cmd = MemCmd::WriteLineReq;
303 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
304 }
305}
306
307void
308Cache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time)
309{

--- 1080 unchanged lines hidden ---