| cache.cc (13478:59414c401cd9) | cache.cc (13564:9bbd53a77887) |
|---|---|
| 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 377 unchanged lines hidden (view full) --- 386 assert(pf->getAddr() == pkt->getAddr()); 387 assert(pf->getSize() == pkt->getSize()); 388 } 389 390 pkt->makeTimingResponse(); 391 392 // request_time is used here, taking into account lat and the delay 393 // charged if the packet comes from the xbar. | 1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 377 unchanged lines hidden (view full) --- 386 assert(pf->getAddr() == pkt->getAddr()); 387 assert(pf->getSize() == pkt->getSize()); 388 } 389 390 pkt->makeTimingResponse(); 391 392 // request_time is used here, taking into account lat and the delay 393 // charged if the packet comes from the xbar. |
| 394 cpuSidePort.schedTimingResp(pkt, request_time, true); | 394 cpuSidePort.schedTimingResp(pkt, request_time); |
| 395 396 // If an outstanding request is in progress (we found an 397 // MSHR) this is set to null 398 pkt = pf; 399 } 400 401 BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time); 402} --- 394 unchanged lines hidden (view full) --- 797 // propagate that. Response should not have 798 // isInvalidate() set otherwise. 799 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 800 DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 801 tgt_pkt->print()); 802 } 803 // Reset the bus additional time as it is now accounted for 804 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; | 395 396 // If an outstanding request is in progress (we found an 397 // MSHR) this is set to null 398 pkt = pf; 399 } 400 401 BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time); 402} --- 394 unchanged lines hidden (view full) --- 797 // propagate that. Response should not have 798 // isInvalidate() set otherwise. 799 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 800 DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 801 tgt_pkt->print()); 802 } 803 // Reset the bus additional time as it is now accounted for 804 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; |
| 805 cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true); | 805 cpuSidePort.schedTimingResp(tgt_pkt, completion_time); |
| 806 break; 807 808 case MSHR::Target::FromPrefetcher: 809 assert(tgt_pkt->cmd == MemCmd::HardPFReq); 810 if (blk) 811 blk->status |= BlkHWPrefetched; 812 delete tgt_pkt; 813 break; --- 113 unchanged lines hidden (view full) --- 927 // Here we consider forward_time, paying for just forward latency and 928 // also charging the delay provided by the xbar. 929 // forward_time is used as send_time in next allocateWriteBuffer(). 930 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 931 // Here we reset the timing of the packet. 932 pkt->headerDelay = pkt->payloadDelay = 0; 933 DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 934 pkt->print(), forward_time); | 806 break; 807 808 case MSHR::Target::FromPrefetcher: 809 assert(tgt_pkt->cmd == MemCmd::HardPFReq); 810 if (blk) 811 blk->status |= BlkHWPrefetched; 812 delete tgt_pkt; 813 break; --- 113 unchanged lines hidden (view full) --- 927 // Here we consider forward_time, paying for just forward latency and 928 // also charging the delay provided by the xbar. 929 // forward_time is used as send_time in next allocateWriteBuffer(). 930 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 931 // Here we reset the timing of the packet. 932 pkt->headerDelay = pkt->payloadDelay = 0; 933 DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 934 pkt->print(), forward_time); |
| 935 memSidePort.schedTimingSnoopResp(pkt, forward_time, true); | 935 memSidePort.schedTimingSnoopResp(pkt, forward_time); |
| 936} 937 938uint32_t 939Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 940 bool is_deferred, bool pending_inval) 941{ 942 DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 943 // deferred snoops can only happen in timing mode --- 459 unchanged lines hidden --- | 936} 937 938uint32_t 939Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 940 bool is_deferred, bool pending_inval) 941{ 942 DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 943 // deferred snoops can only happen in timing mode --- 459 unchanged lines hidden --- |