cache.cc (12749:223c83ed9979) cache.cc (12794:ba78a382b0f6)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 660 unchanged lines hidden (view full) ---

669Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
670 PacketList &writebacks)
671{
672 MSHR::Target *initial_tgt = mshr->getTarget();
673 // First offset for critical word first calculations
674 const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
675
676 const bool is_error = pkt->isError();
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 660 unchanged lines hidden (view full) ---

669Cache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk,
670 PacketList &writebacks)
671{
672 MSHR::Target *initial_tgt = mshr->getTarget();
673 // First offset for critical word first calculations
674 const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
675
676 const bool is_error = pkt->isError();
677 bool is_fill = !mshr->isForward &&
678 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
679 // allow invalidation responses originating from write-line
680 // requests to be discarded
681 bool is_invalidate = pkt->isInvalidate();
682
683 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
684 for (auto &target: targets) {
685 Packet *tgt_pkt = target.pkt;
686 switch (target.source) {

--- 24 unchanged lines hidden (view full) ---

711 // we got the block in a writable state, so promote
712 // any deferred targets if possible
713 mshr->promoteWritable();
714 // NB: we use the original packet here and not the response!
715 blk = handleFill(tgt_pkt, blk, writebacks,
716 targets.allocOnFill);
717 assert(blk);
718
677 // allow invalidation responses originating from write-line
678 // requests to be discarded
679 bool is_invalidate = pkt->isInvalidate();
680
681 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
682 for (auto &target: targets) {
683 Packet *tgt_pkt = target.pkt;
684 switch (target.source) {

--- 24 unchanged lines hidden (view full) ---

709 // we got the block in a writable state, so promote
710 // any deferred targets if possible
711 mshr->promoteWritable();
712 // NB: we use the original packet here and not the response!
713 blk = handleFill(tgt_pkt, blk, writebacks,
714 targets.allocOnFill);
715 assert(blk);
716
719 // treat as a fill, and discard the invalidation
720 // response
721 is_fill = true;
717 // discard the invalidation response
722 is_invalidate = false;
723 }
724
718 is_invalidate = false;
719 }
720
725 if (is_fill) {
721 if (blk && blk->isValid() && !mshr->isForward) {
726 satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade());
727
728 // How many bytes past the first request is this one
729 int transfer_offset =
730 tgt_pkt->getOffset(blkSize) - initial_offset;
731 if (transfer_offset < 0) {
732 transfer_offset += blkSize;
733 }

--- 671 unchanged lines hidden ---
722 satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade());
723
724 // How many bytes past the first request is this one
725 int transfer_offset =
726 tgt_pkt->getOffset(blkSize) - initial_offset;
727 if (transfer_offset < 0) {
728 transfer_offset += blkSize;
729 }

--- 671 unchanged lines hidden ---