cache.cc (12600:e670dd17c8cf) cache.cc (12630:2208bf99bffd)
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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643 // Cache line clearing instructions
644 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
645 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
646 pkt->cmd = MemCmd::WriteLineReq;
647 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
648 }
649}
650
1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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643 // Cache line clearing instructions
644 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
645 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
646 pkt->cmd = MemCmd::WriteLineReq;
647 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
648 }
649}
650
651bool
651void
652Cache::recvTimingReq(PacketPtr pkt)
653{
654 DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
655
656 assert(pkt->isRequest());
657
658 // Just forward the packet if caches are disabled.
659 if (system->bypassCaches()) {
660 // @todo This should really enqueue the packet rather
661 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
662 assert(success);
652Cache::recvTimingReq(PacketPtr pkt)
653{
654 DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
655
656 assert(pkt->isRequest());
657
658 // Just forward the packet if caches are disabled.
659 if (system->bypassCaches()) {
660 // @todo This should really enqueue the packet rather
661 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
662 assert(success);
663 return true;
663 return;
664 }
665
666 promoteWholeLineWrites(pkt);
667
668 // Cache maintenance operations have to visit all the caches down
669 // to the specified xbar (PoC, PoU, etc.). Even if a cache above
670 // is responding we forward the packet to the memory below rather
671 // than creating an express snoop.

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725 // the sending cache is still relying on the packet
726 pendingDelete.reset(pkt);
727
728 // no need to take any further action in this particular cache
729 // as an upstram cache has already committed to responding,
730 // and we have already sent out any express snoops in the
731 // section above to ensure all other copies in the system are
732 // invalidated
664 }
665
666 promoteWholeLineWrites(pkt);
667
668 // Cache maintenance operations have to visit all the caches down
669 // to the specified xbar (PoC, PoU, etc.). Even if a cache above
670 // is responding we forward the packet to the memory below rather
671 // than creating an express snoop.

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725 // the sending cache is still relying on the packet
726 pendingDelete.reset(pkt);
727
728 // no need to take any further action in this particular cache
729 // as an upstram cache has already committed to responding,
730 // and we have already sent out any express snoops in the
731 // section above to ensure all other copies in the system are
732 // invalidated
733 return true;
733 return;
734 }
735
736 // anything that is merely forwarded pays for the forward latency and
737 // the delay provided by the crossbar
738 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
739
740 // We use lookupLatency here because it is used to specify the latency
741 // to access.

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971 !pkt->req->isCacheMaintenance())
972 next_pf_time = prefetcher->notify(pkt);
973 }
974 }
975 }
976
977 if (next_pf_time != MaxTick)
978 schedMemSideSendEvent(next_pf_time);
734 }
735
736 // anything that is merely forwarded pays for the forward latency and
737 // the delay provided by the crossbar
738 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
739
740 // We use lookupLatency here because it is used to specify the latency
741 // to access.

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971 !pkt->req->isCacheMaintenance())
972 next_pf_time = prefetcher->notify(pkt);
973 }
974 }
975 }
976
977 if (next_pf_time != MaxTick)
978 schedMemSideSendEvent(next_pf_time);
979
980 return true;
981}
982
983PacketPtr
984Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
985 bool needsWritable) const
986{
987 // should never see evictions here
988 assert(!cpu_pkt->isEviction());

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2765}
2766
2767bool
2768Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2769{
2770 assert(!cache->system->bypassCaches());
2771
2772 // always let express snoop packets through if even if blocked
979}
980
981PacketPtr
982Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
983 bool needsWritable) const
984{
985 // should never see evictions here
986 assert(!cpu_pkt->isEviction());

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2763}
2764
2765bool
2766Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2767{
2768 assert(!cache->system->bypassCaches());
2769
2770 // always let express snoop packets through if even if blocked
2773 if (pkt->isExpressSnoop()) {
2774 bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
2775 assert(bypass_success);
2771 if (pkt->isExpressSnoop() || tryTiming(pkt)) {
2772 cache->recvTimingReq(pkt);
2776 return true;
2777 }
2773 return true;
2774 }
2778
2779 return tryTiming(pkt) && cache->recvTimingReq(pkt);
2775 return false;
2780}
2781
2782Tick
2783Cache::CpuSidePort::recvAtomic(PacketPtr pkt)
2784{
2785 return cache->recvAtomic(pkt);
2786}
2787

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2777
2778Tick
2779Cache::CpuSidePort::recvAtomic(PacketPtr pkt)
2780{
2781 return cache->recvAtomic(pkt);
2782}
2783

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