cache.cc (12084:5a3769ff3d55) cache.cc (12167:24eb63c709c2)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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2414 mshr->blkAddr);
2415
2416 // Deallocate the mshr target
2417 if (mshrQueue.forceDeallocateTarget(mshr)) {
2418 // Clear block if this deallocation resulted freed an
2419 // mshr when all had previously been utilized
2420 clearBlocked(Blocked_NoMSHRs);
2421 }
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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2414 mshr->blkAddr);
2415
2416 // Deallocate the mshr target
2417 if (mshrQueue.forceDeallocateTarget(mshr)) {
2418 // Clear block if this deallocation resulted freed an
2419 // mshr when all had previously been utilized
2420 clearBlocked(Blocked_NoMSHRs);
2421 }
2422
2423 // given that no response is expected, delete Request and Packet
2424 delete tgt_pkt->req;
2425 delete tgt_pkt;
2426
2422 return false;
2423 }
2424 }
2425
2426 // either a prefetch that is not present upstream, or a normal
2427 // MSHR request, proceed to get the packet to send downstream
2428 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
2429

--- 243 unchanged lines hidden --- 		2427 return false;
2428 }
2429 }
2430
2431 // either a prefetch that is not present upstream, or a normal
2432 // MSHR request, proceed to get the packet to send downstream
2433 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
2434

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