cache.cc (11751:cd6248b276a8) cache.cc (11830:79c3f6a60392)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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580 pkt->cmd = MemCmd::WriteLineReq;
581 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
582 }
583}
584
585bool
586Cache::recvTimingReq(PacketPtr pkt)
587{
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 571 unchanged lines hidden (view full) ---

580 pkt->cmd = MemCmd::WriteLineReq;
581 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
582 }
583}
584
585bool
586Cache::recvTimingReq(PacketPtr pkt)
587{
588 DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print());
588 DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
589
590 assert(pkt->isRequest());
591
592 // Just forward the packet if caches are disabled.
593 if (system->bypassCaches()) {
594 // @todo This should really enqueue the packet rather
595 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
596 assert(success);

--- 2076 unchanged lines hidden --- 		589
590 assert(pkt->isRequest());
591
592 // Just forward the packet if caches are disabled.
593 if (system->bypassCaches()) {
594 // @todo This should really enqueue the packet rather
595 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
596 assert(success);

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