cache.cc (11745:3102db8903f5) cache.cc (11747:a6da15219f95)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 910 unchanged lines hidden (view full) ---

919 assert(cpu_pkt->needsResponse());
920
921 MemCmd cmd;
922 // @TODO make useUpgrades a parameter.
923 // Note that ownership protocols require upgrade, otherwise a
924 // write miss on a shared owned block will generate a ReadExcl,
925 // which will clobber the owned copy.
926 const bool useUpgrades = true;
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 910 unchanged lines hidden (view full) ---

919 assert(cpu_pkt->needsResponse());
920
921 MemCmd cmd;
922 // @TODO make useUpgrades a parameter.
923 // Note that ownership protocols require upgrade, otherwise a
924 // write miss on a shared owned block will generate a ReadExcl,
925 // which will clobber the owned copy.
926 const bool useUpgrades = true;
927 if (blkValid && useUpgrades) {
927 if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
928 assert(!blkValid || !blk->isWritable());
929 // forward as invalidate to all other caches, this gives us
930 // the line in Exclusive state, and invalidates all other
931 // copies
932 cmd = MemCmd::InvalidateReq;
933 } else if (blkValid && useUpgrades) {
928 // only reason to be here is that blk is read only and we need
929 // it to be writable
930 assert(needsWritable);
931 assert(!blk->isWritable());
932 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
933 } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
934 cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
935 // Even though this SC will fail, we still need to send out the
936 // request and get the data to supply it to other snoopers in the case
937 // where the determination the StoreCond fails is delayed due to
938 // all caches not being on the same local bus.
939 cmd = MemCmd::SCUpgradeFailReq;
934 // only reason to be here is that blk is read only and we need
935 // it to be writable
936 assert(needsWritable);
937 assert(!blk->isWritable());
938 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
939 } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
940 cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
941 // Even though this SC will fail, we still need to send out the
942 // request and get the data to supply it to other snoopers in the case
943 // where the determination the StoreCond fails is delayed due to
944 // all caches not being on the same local bus.
945 cmd = MemCmd::SCUpgradeFailReq;
940 } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
941 // forward as invalidate to all other caches, this gives us
942 // the line in Exclusive state, and invalidates all other
943 // copies
944 cmd = MemCmd::InvalidateReq;
945 } else {
946 // block is invalid
947 cmd = needsWritable ? MemCmd::ReadExReq :
948 (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
949 }
950 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
951
952 // if there are upstream caches that have already marked the

--- 1701 unchanged lines hidden --- 		946 } else {
947 // block is invalid
948 cmd = needsWritable ? MemCmd::ReadExReq :
949 (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
950 }
951 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
952
953 // if there are upstream caches that have already marked the

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