cache.cc (11452:4bc3a0c0861c) cache.cc (11453:dd9763792521)
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1221// Response handling: responses from the memory side
1222//
1223/////////////////////////////////////////////////////
1224
1225
1226void
1227Cache::handleUncacheableWriteResp(PacketPtr pkt)
1228{
1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1221// Response handling: responses from the memory side
1222//
1223/////////////////////////////////////////////////////
1224
1225
1226void
1227Cache::handleUncacheableWriteResp(PacketPtr pkt)
1228{
1229 WriteQueueEntry *wq_entry =
1230 dynamic_cast<WriteQueueEntry*>(pkt->senderState);
1231 assert(wq_entry);
1232
1233 WriteQueueEntry::Target *target = wq_entry->getTarget();
1234 Packet *tgt_pkt = target->pkt;
1235
1236 // we send out invalidation reqs and get invalidation
1237 // responses for write-line requests
1238 assert(tgt_pkt->cmd != MemCmd::WriteLineReq);
1239
1240 int stats_cmd_idx = tgt_pkt->cmdToIndex();
1241 Tick miss_latency = curTick() - target->recvTime;
1242 assert(pkt->req->masterId() < system->maxMasters());
1243 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
1244 miss_latency;
1245
1246 tgt_pkt->makeTimingResponse();
1247 // if this packet is an error copy that to the new packet
1248 if (pkt->isError())
1249 tgt_pkt->copyError(pkt);
1250 // Reset the bus additional time as it is now accounted for
1251 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
1252 Tick completion_time = clockEdge(responseLatency) +
1253 pkt->headerDelay + pkt->payloadDelay;
1254
1229 Tick completion_time = clockEdge(responseLatency) +
1230 pkt->headerDelay + pkt->payloadDelay;
1231
1255 cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
1232 // Reset the bus additional time as it is now accounted for
1233 pkt->headerDelay = pkt->payloadDelay = 0;
1256
1234
1257 wq_entry->popTarget();
1258 assert(!wq_entry->hasTargets());
1259
1260 bool wasFull = writeBuffer.isFull();
1261 writeBuffer.deallocate(wq_entry);
1262
1263 if (wasFull && !writeBuffer.isFull()) {
1264 clearBlocked(Blocked_NoWBBuffers);
1265 }
1266
1267 delete pkt;
1235 cpuSidePort->schedTimingResp(pkt, completion_time, true);
1268}
1269
1270void
1271Cache::recvTimingResp(PacketPtr pkt)
1272{
1273 assert(pkt->isResponse());
1274
1275 // all header delay should be paid for by the crossbar, unless

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1294 if (pkt->isWrite()) {
1295 assert(pkt->req->isUncacheable());
1296 handleUncacheableWriteResp(pkt);
1297 return;
1298 }
1299
1300 // we have dealt with any (uncacheable) writes above, from here on
1301 // we know we are dealing with an MSHR due to a miss or a prefetch
1236}
1237
1238void
1239Cache::recvTimingResp(PacketPtr pkt)
1240{
1241 assert(pkt->isResponse());
1242
1243 // all header delay should be paid for by the crossbar, unless

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1262 if (pkt->isWrite()) {
1263 assert(pkt->req->isUncacheable());
1264 handleUncacheableWriteResp(pkt);
1265 return;
1266 }
1267
1268 // we have dealt with any (uncacheable) writes above, from here on
1269 // we know we are dealing with an MSHR due to a miss or a prefetch
1302 MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
1270 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
1303 assert(mshr);
1304
1305 if (mshr == noTargetMSHR) {
1306 // we always clear at least one target
1307 clearBlocked(Blocked_NoTargets);
1308 noTargetMSHR = NULL;
1309 }
1310

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2243{
2244 // Check both MSHR queue and write buffer for potential requests,
2245 // note that null does not mean there is no request, it could
2246 // simply be that it is not ready
2247 MSHR *miss_mshr = mshrQueue.getNext();
2248 WriteQueueEntry *wq_entry = writeBuffer.getNext();
2249
2250 // If we got a write buffer request ready, first priority is a
1271 assert(mshr);
1272
1273 if (mshr == noTargetMSHR) {
1274 // we always clear at least one target
1275 clearBlocked(Blocked_NoTargets);
1276 noTargetMSHR = NULL;
1277 }
1278

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2211{
2212 // Check both MSHR queue and write buffer for potential requests,
2213 // note that null does not mean there is no request, it could
2214 // simply be that it is not ready
2215 MSHR *miss_mshr = mshrQueue.getNext();
2216 WriteQueueEntry *wq_entry = writeBuffer.getNext();
2217
2218 // If we got a write buffer request ready, first priority is a
2251 // full write buffer (but only if we have no uncacheable write
2252 // responses outstanding, possibly revisit this last part),
2253 // otherwhise we favour the miss requests
2254 if (wq_entry &&
2255 ((writeBuffer.isFull() && writeBuffer.numInService() == 0) ||
2256 !miss_mshr)) {
2219 // full write buffer, otherwise we favour the miss requests
2220 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
2257 // need to search MSHR queue for conflicting earlier miss.
2258 MSHR *conflict_mshr =
2259 mshrQueue.findPending(wq_entry->blkAddr,
2260 wq_entry->isSecure);
2261
2262 if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
2263 // Service misses in order until conflict is cleared.
2264 return conflict_mshr;

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2496
2497 // always a single target for write queue entries
2498 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
2499
2500 DPRINTF(Cache, "%s write %s for addr %#llx size %d\n", __func__,
2501 tgt_pkt->cmdString(), tgt_pkt->getAddr(),
2502 tgt_pkt->getSize());
2503
2221 // need to search MSHR queue for conflicting earlier miss.
2222 MSHR *conflict_mshr =
2223 mshrQueue.findPending(wq_entry->blkAddr,
2224 wq_entry->isSecure);
2225
2226 if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
2227 // Service misses in order until conflict is cleared.
2228 return conflict_mshr;

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2460
2461 // always a single target for write queue entries
2462 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
2463
2464 DPRINTF(Cache, "%s write %s for addr %#llx size %d\n", __func__,
2465 tgt_pkt->cmdString(), tgt_pkt->getAddr(),
2466 tgt_pkt->getSize());
2467
2504 PacketPtr pkt = nullptr;
2505 bool delete_pkt = false;
2506
2507 if (tgt_pkt->isEviction()) {
2508 assert(!wq_entry->isUncacheable());
2509 // no response expected, just forward packet as it is
2510 pkt = tgt_pkt;
2511 } else {
2512 // the only thing we deal with besides eviction commands
2513 // are uncacheable writes
2514 assert(tgt_pkt->req->isUncacheable() && tgt_pkt->isWrite());
2515 // not a cache block request, but a response is expected
2516 // make copy of current packet to forward, keep current
2517 // copy for response handling
2518 pkt = new Packet(tgt_pkt, false, true);
2519 pkt->setData(tgt_pkt->getConstPtr<uint8_t>());
2520 delete_pkt = true;
2521 }
2522
2523 pkt->pushSenderState(wq_entry);
2524
2525 if (!memSidePort->sendTimingReq(pkt)) {
2526 if (delete_pkt) {
2527 // we are awaiting a retry, but we
2528 // delete the packet and will be creating a new packet
2529 // when we get the opportunity
2530 delete pkt;
2531 }
2468 // forward as is, both for evictions and uncacheable writes
2469 if (!memSidePort->sendTimingReq(tgt_pkt)) {
2532 // note that we have now masked any requestBus and
2533 // schedSendEvent (we will wait for a retry before
2534 // doing anything), and this is so even if we do not
2535 // care about this packet and might override it before
2536 // it gets retried
2537 return true;
2538 } else {
2539 markInService(wq_entry);

--- 182 unchanged lines hidden --- 		2470 // note that we have now masked any requestBus and
2471 // schedSendEvent (we will wait for a retry before
2472 // doing anything), and this is so even if we do not
2473 // care about this packet and might override it before
2474 // it gets retried
2475 return true;
2476 } else {
2477 markInService(wq_entry);

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