cache.cc (11332:40bcb0e97de9) cache.cc (11333:c41d552d6f2e)
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1006}
1007
1008
1009Tick
1010Cache::recvAtomic(PacketPtr pkt)
1011{
1012 // We are in atomic mode so we pay just for lookupLatency here.
1013 Cycles lat = lookupLatency;
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 997 unchanged lines hidden (view full) ---

1006}
1007
1008
1009Tick
1010Cache::recvAtomic(PacketPtr pkt)
1011{
1012 // We are in atomic mode so we pay just for lookupLatency here.
1013 Cycles lat = lookupLatency;
1014 // @TODO: make this a parameter
1015 bool last_level_cache = false;
1016
1017 // Forward the request if the system is in cache bypass mode.
1018 if (system->bypassCaches())
1019 return ticksToCycles(memSidePort->sendAtomic(pkt));
1020
1021 promoteWholeLineWrites(pkt);
1022
1014
1015 // Forward the request if the system is in cache bypass mode.
1016 if (system->bypassCaches())
1017 return ticksToCycles(memSidePort->sendAtomic(pkt));
1018
1019 promoteWholeLineWrites(pkt);
1020
1021 // follow the same flow as in recvTimingReq, and check if a cache
1022 // above us is responding
1023 if (pkt->cacheResponding()) {
1023 if (pkt->cacheResponding()) {
1024 // have to invalidate ourselves and any lower caches even if
1025 // upper cache will be responding
1026 if (pkt->isInvalidate()) {
1027 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1028 if (blk && blk->isValid()) {
1029 tags->invalidate(blk);
1030 blk->invalidate();
1031 DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):"
1032 " invalidating\n",
1033 pkt->cmdString(), pkt->getAddr(),
1034 pkt->isSecure() ? "s" : "ns");
1035 }
1036 if (!last_level_cache) {
1037 DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):"
1038 " forwarding\n",
1039 pkt->cmdString(), pkt->getAddr(),
1040 pkt->isSecure() ? "s" : "ns");
1041 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1042 }
1043 } else {
1044 DPRINTF(Cache, "Other cache responding to %s on %#llx: "
1045 "not responding\n",
1046 pkt->cmdString(), pkt->getAddr());
1024 DPRINTF(Cache, "Cache above responding to %#llx (%s): "
1025 "not responding\n",
1026 pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
1027
1028 // if a cache is responding, and it had the line in Owned
1029 // rather than Modified state, we need to invalidate any
1030 // copies that are not on the same path to memory
1031 if (pkt->needsWritable() && !pkt->responderHadWritable()) {
1032 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1047 }
1048
1049 return lat * clockPeriod();
1050 }
1051
1052 // should assert here that there are no outstanding MSHRs or
1053 // writebacks... that would mean that someone used an atomic
1054 // access in timing mode

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1034
1035 return lat * clockPeriod();
1036 }
1037
1038 // should assert here that there are no outstanding MSHRs or
1039 // writebacks... that would mean that someone used an atomic
1040 // access in timing mode

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