cache.cc (11177:524c44cf8278) cache.cc (11190:0964165d1857)
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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537 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
538 }
539}
540
541bool
542Cache::recvTimingReq(PacketPtr pkt)
543{
544 DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print());
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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537 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
538 }
539}
540
541bool
542Cache::recvTimingReq(PacketPtr pkt)
543{
544 DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print());
545//@todo Add back in MemDebug Calls
546// MemDebug::cacheAccess(pkt);
547
545
548
549 /// @todo temporary hack to deal with memory corruption issue until
550 /// 4-phase transactions are complete
551 for (int x = 0; x < pendingDelete.size(); x++)
552 delete pendingDelete[x];
553 pendingDelete.clear();
554
555 assert(pkt->isRequest());
556
557 // Just forward the packet if caches are disabled.
558 if (system->bypassCaches()) {
559 // @todo This should really enqueue the packet rather
560 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
561 assert(success);
562 return true;

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597 // every cache in the system
598 bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt);
599 // express snoops always succeed
600 assert(success);
601
602 // main memory will delete the packet
603 }
604
546 assert(pkt->isRequest());
547
548 // Just forward the packet if caches are disabled.
549 if (system->bypassCaches()) {
550 // @todo This should really enqueue the packet rather
551 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
552 assert(success);
553 return true;

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588 // every cache in the system
589 bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt);
590 // express snoops always succeed
591 assert(success);
592
593 // main memory will delete the packet
594 }
595
605 /// @todo nominally we should just delete the packet here,
606 /// however, until 4-phase stuff we can't because sending
607 /// cache is still relying on it.
608 pendingDelete.push_back(pkt);
596 // queue for deletion, as the sending cache is still relying
597 // on the packet
598 pendingDelete.reset(pkt);
609
610 // no need to take any action in this particular cache as the
611 // caches along the path to memory are allowed to keep lines
612 // in a shared state, and a cache above us already committed
613 // to responding
614 return true;
615 }
616

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673
674 // In this case we are considering request_time that takes
675 // into account the delay of the xbar, if any, and just
676 // lat, neglecting responseLatency, modelling hit latency
677 // just as lookupLatency or or the value of lat overriden
678 // by access(), that calls accessBlock() function.
679 cpuSidePort->schedTimingResp(pkt, request_time);
680 } else {
599
600 // no need to take any action in this particular cache as the
601 // caches along the path to memory are allowed to keep lines
602 // in a shared state, and a cache above us already committed
603 // to responding
604 return true;
605 }
606

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663
664 // In this case we are considering request_time that takes
665 // into account the delay of the xbar, if any, and just
666 // lat, neglecting responseLatency, modelling hit latency
667 // just as lookupLatency or or the value of lat overriden
668 // by access(), that calls accessBlock() function.
669 cpuSidePort->schedTimingResp(pkt, request_time);
670 } else {
681 /// @todo nominally we should just delete the packet here,
682 /// however, until 4-phase stuff we can't because sending cache is
683 /// still relying on it. If the block is found in access(),
684 /// CleanEvict and Writeback messages will be deleted here as
685 /// well.
686 pendingDelete.push_back(pkt);
671 // queue the packet for deletion, as the sending cache is
672 // still relying on it; if the block is found in access(),
673 // CleanEvict and Writeback messages will be deleted
674 // here as well
675 pendingDelete.reset(pkt);
687 }
688 } else {
689 // miss
690
691 Addr blk_addr = blockAlign(pkt->getAddr());
692
693 // ignore any existing MSHR if we are dealing with an
694 // uncacheable request

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749 //@todo remove hw_pf here
750
751 // Coalesce unless it was a software prefetch (see above).
752 if (pkt) {
753 assert(pkt->cmd != MemCmd::Writeback);
754 // CleanEvicts corresponding to blocks which have outstanding
755 // requests in MSHRs can be deleted here.
756 if (pkt->cmd == MemCmd::CleanEvict) {
676 }
677 } else {
678 // miss
679
680 Addr blk_addr = blockAlign(pkt->getAddr());
681
682 // ignore any existing MSHR if we are dealing with an
683 // uncacheable request

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738 //@todo remove hw_pf here
739
740 // Coalesce unless it was a software prefetch (see above).
741 if (pkt) {
742 assert(pkt->cmd != MemCmd::Writeback);
743 // CleanEvicts corresponding to blocks which have outstanding
744 // requests in MSHRs can be deleted here.
745 if (pkt->cmd == MemCmd::CleanEvict) {
757 pendingDelete.push_back(pkt);
746 pendingDelete.reset(pkt);
758 } else {
759 DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n",
760 __func__, pkt->cmdString(), pkt->getAddr(),
761 pkt->getSize());
762
763 assert(pkt->req->masterId() < system->maxMasters());
764 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
765 if (mshr->threadNum != 0/*pkt->req->threadId()*/) {

--- 1783 unchanged lines hidden --- 		747 } else {
748 DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n",
749 __func__, pkt->cmdString(), pkt->getAddr(),
750 pkt->getSize());
751
752 assert(pkt->req->masterId() < system->maxMasters());
753 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
754 if (mshr->threadNum != 0/*pkt->req->threadId()*/) {

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