cache.cc (11137:0229c7b15ca1) cache.cc (11177:524c44cf8278)
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1185 if (mshr == noTargetMSHR) {
1186 // we always clear at least one target
1187 clearBlocked(Blocked_NoTargets);
1188 noTargetMSHR = NULL;
1189 }
1190
1191 // Initial target is used just for stats
1192 MSHR::Target *initial_tgt = mshr->getTarget();
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1185 if (mshr == noTargetMSHR) {
1186 // we always clear at least one target
1187 clearBlocked(Blocked_NoTargets);
1188 noTargetMSHR = NULL;
1189 }
1190
1191 // Initial target is used just for stats
1192 MSHR::Target *initial_tgt = mshr->getTarget();
1193 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1194 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
1195 Tick miss_latency = curTick() - initial_tgt->recvTime;
1196 PacketList writebacks;
1197 // We need forward_time here because we have a call of
1198 // allocateWriteBuffer() that need this parameter to specify the
1199 // time to request the bus. In this case we use forward latency
1200 // because there is a writeback. We pay also here for headerDelay
1201 // that is charged of bus latencies if the packet comes from the

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1207 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
1208 miss_latency;
1209 } else {
1210 assert(pkt->req->masterId() < system->maxMasters());
1211 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
1212 miss_latency;
1213 }
1214
1193 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
1194 Tick miss_latency = curTick() - initial_tgt->recvTime;
1195 PacketList writebacks;
1196 // We need forward_time here because we have a call of
1197 // allocateWriteBuffer() that need this parameter to specify the
1198 // time to request the bus. In this case we use forward latency
1199 // because there is a writeback. We pay also here for headerDelay
1200 // that is charged of bus latencies if the packet comes from the

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1206 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
1207 miss_latency;
1208 } else {
1209 assert(pkt->req->masterId() < system->maxMasters());
1210 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
1211 miss_latency;
1212 }
1213
1214 // upgrade deferred targets if we got exclusive
1215 if (!pkt->sharedAsserted()) {
1216 mshr->promoteExclusive();
1217 }
1218
1215 bool is_fill = !mshr->isForward &&
1216 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
1217
1219 bool is_fill = !mshr->isForward &&
1220 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
1221
1222 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1223
1218 if (is_fill && !is_error) {
1219 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
1220 pkt->getAddr());
1221
1224 if (is_fill && !is_error) {
1225 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
1226 pkt->getAddr());
1227
1222 // give mshr a chance to do some dirty work
1223 mshr->handleFill(pkt, blk);
1224
1225 blk = handleFill(pkt, blk, writebacks);
1226 assert(blk != NULL);
1227 }
1228
1229 // allow invalidation responses originating from write-line
1230 // requests to be discarded
1231 bool is_invalidate = pkt->isInvalidate();
1232

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1257 // unlike the other packet flows, where data is found in other
1258 // caches or memory and brought back, write-line requests always
1259 // have the data right away, so the above check for "is fill?"
1260 // cannot actually be determined until examining the stored MSHR
1261 // state. We "catch up" with that logic here, which is duplicated
1262 // from above.
1263 if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
1264 assert(!is_error);
1228 blk = handleFill(pkt, blk, writebacks);
1229 assert(blk != NULL);
1230 }
1231
1232 // allow invalidation responses originating from write-line
1233 // requests to be discarded
1234 bool is_invalidate = pkt->isInvalidate();
1235

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1260 // unlike the other packet flows, where data is found in other
1261 // caches or memory and brought back, write-line requests always
1262 // have the data right away, so the above check for "is fill?"
1263 // cannot actually be determined until examining the stored MSHR
1264 // state. We "catch up" with that logic here, which is duplicated
1265 // from above.
1266 if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
1267 assert(!is_error);
1265
1268 // we got the block in exclusive state, so promote any
1269 // deferred targets if possible
1270 mshr->promoteExclusive();
1266 // NB: we use the original packet here and not the response!
1271 // NB: we use the original packet here and not the response!
1267 mshr->handleFill(tgt_pkt, blk);
1268 blk = handleFill(tgt_pkt, blk, writebacks);
1269 assert(blk != NULL);
1270
1271 // treat as a fill, and discard the invalidation
1272 // response
1273 is_fill = true;
1274 is_invalidate = false;
1275 }

--- 1269 unchanged lines hidden --- 		1272 blk = handleFill(tgt_pkt, blk, writebacks);
1273 assert(blk != NULL);
1274
1275 // treat as a fill, and discard the invalidation
1276 // response
1277 is_fill = true;
1278 is_invalidate = false;
1279 }

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