cache.cc (11051:81b1f46061c8) cache.cc (11053:62544e45c0f4)
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 49 unchanged lines hidden (view full) ---

58#include "debug/Cache.hh"
59#include "debug/CachePort.hh"
60#include "debug/CacheTags.hh"
61#include "mem/cache/blk.hh"
62#include "mem/cache/mshr.hh"
63#include "mem/cache/prefetch/base.hh"
64#include "sim/sim_exit.hh"
65
1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 49 unchanged lines hidden (view full) ---

58#include "debug/Cache.hh"
59#include "debug/CachePort.hh"
60#include "debug/CacheTags.hh"
61#include "mem/cache/blk.hh"
62#include "mem/cache/mshr.hh"
63#include "mem/cache/prefetch/base.hh"
64#include "sim/sim_exit.hh"
65
66Cache::Cache(const Params *p)
67 : BaseCache(p),
66Cache::Cache(const CacheParams *p)
67 : BaseCache(p, p->system->cacheLineSize()),
68 tags(p->tags),
69 prefetcher(p->prefetcher),
70 doFastWrites(true),
71 prefetchOnAccess(p->prefetch_on_access)
72{
73 tempBlock = new CacheBlk();
74 tempBlock->data = new uint8_t[blkSize];
75

--- 2301 unchanged lines hidden (view full) ---

2377
2378Cache::
2379CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
2380 const std::string &_label)
2381 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
2382{
2383}
2384
68 tags(p->tags),
69 prefetcher(p->prefetcher),
70 doFastWrites(true),
71 prefetchOnAccess(p->prefetch_on_access)
72{
73 tempBlock = new CacheBlk();
74 tempBlock->data = new uint8_t[blkSize];
75

--- 2301 unchanged lines hidden (view full) ---

2377
2378Cache::
2379CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
2380 const std::string &_label)
2381 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
2382{
2383}
2384
2385Cache*
2386CacheParams::create()
2387{
2388 assert(tags);
2389
2390 return new Cache(this);
2391}
2385///////////////
2386//
2387// MemSidePort
2388//
2389///////////////
2390
2391bool
2392Cache::MemSidePort::recvTimingResp(PacketPtr pkt)

--- 118 unchanged lines hidden --- 		2392///////////////
2393//
2394// MemSidePort
2395//
2396///////////////
2397
2398bool
2399Cache::MemSidePort::recvTimingResp(PacketPtr pkt)

--- 118 unchanged lines hidden ---