1/* 2 * Copyright (c) 2010-2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 546 unchanged lines hidden (view full) --- 555 pkt->allocate(); 556 DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 557 cpu_pkt->print()); 558 return pkt; 559} 560 561 562Cycles |
563Cache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, |
564 PacketList &writebacks) 565{ 566 // deal with the packets that go through the write path of 567 // the cache, i.e. any evictions and writes 568 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 569 (pkt->req->isUncacheable() && pkt->isWrite())) { 570 Cycles latency = ticksToCycles(memSidePort.sendAtomic(pkt)); 571 --- 829 unchanged lines hidden --- |