906,907d905
<
< // See comment in cache.hh.
909,910c907,908
< Cache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
< bool needsWritable) const
---
> Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
> bool needsWritable) const
911a910,912
> // should never see evictions here
> assert(!cpu_pkt->isEviction());
>
914,920c915,919
< if (cpu_pkt->req->isUncacheable()) {
< // note that at the point we see the uncacheable request we
< // flush any block, but there could be an outstanding MSHR,
< // and the cache could have filled again before we actually
< // send out the forwarded uncacheable request (blk could thus
< // be non-null)
< return NULL;
---
> if (cpu_pkt->req->isUncacheable() ||
> (!blkValid && cpu_pkt->isUpgrade())) {
> // uncacheable requests and upgrades from upper-level caches
> // that missed completely just go through as is
> return nullptr;
923,931d921
< if (!blkValid &&
< (cpu_pkt->isUpgrade() ||
< cpu_pkt->isEviction())) {
< // Writebacks that weren't allocated in access() and upgrades
< // from upper-level caches that missed completely just go
< // through.
< return NULL;
< }
<
1035c1025,1032
< PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsWritable());
---
> // deal with the packets that go through the write path of
> // the cache, i.e. any evictions and uncacheable writes
> if (pkt->isEviction() ||
> (pkt->req->isUncacheable() && pkt->isWrite())) {
> lat += ticksToCycles(memSidePort->sendAtomic(pkt));
> return lat * clockPeriod();
> }
> // only misses left
1036a1034,1035
> PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
>
1054a1054,1055
> bool is_invalidate = bus_pkt->isInvalidate();
>
1071,1076d1071
< } else if (pkt->cmd == MemCmd::InvalidateReq) {
< if (blk) {
< // invalidate response to a cache that received
< // an invalidate request
< satisfyCpuSideRequest(pkt, blk);
< }
1083a1079,1080
> assert(blk != NULL);
> is_invalidate = false;
1099a1097,1100
>
> if (is_invalidate && blk && blk->isValid()) {
> invalidateBlock(blk);
> }
2448c2449
< PacketPtr pkt = getBusPacket(tgt_pkt, blk, mshr->needsWritable());
---
> PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());