1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 * Nathan Binkert
44 * Steve Reinhardt
45 * Ron Dreslinski
46 * Andreas Sandberg
47 */
48
49/**
50 * @file
51 * Cache definitions.
52 */
53
54#include "mem/cache/cache.hh"
55
56#include "base/misc.hh"
57#include "base/types.hh"
58#include "debug/Cache.hh"
59#include "debug/CachePort.hh"
60#include "debug/CacheTags.hh"
61#include "debug/CacheVerbose.hh"
62#include "mem/cache/blk.hh"
63#include "mem/cache/mshr.hh"
64#include "mem/cache/prefetch/base.hh"
65#include "sim/sim_exit.hh"
66
67Cache::Cache(const CacheParams *p)
68 : BaseCache(p, p->system->cacheLineSize()),
69 tags(p->tags),
70 prefetcher(p->prefetcher),
71 doFastWrites(true),
72 prefetchOnAccess(p->prefetch_on_access),
73 clusivity(p->clusivity),
74 writebackClean(p->writeback_clean),
75 tempBlockWriteback(nullptr),
76 writebackTempBlockAtomicEvent(this, false,
77 EventBase::Delayed_Writeback_Pri)
78{
79 tempBlock = new CacheBlk();
80 tempBlock->data = new uint8_t[blkSize];
81
82 cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
83 "CpuSidePort");
84 memSidePort = new MemSidePort(p->name + ".mem_side", this,
85 "MemSidePort");
86
87 tags->setCache(this);
88 if (prefetcher)
89 prefetcher->setCache(this);
90}
91
92Cache::~Cache()
93{
94 delete [] tempBlock->data;
95 delete tempBlock;
96
97 delete cpuSidePort;
98 delete memSidePort;
99}
100
101void
102Cache::regStats()
103{
104 BaseCache::regStats();
105}
106
107void
108Cache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
109{
110 assert(pkt->isRequest());
111
112 uint64_t overwrite_val;
113 bool overwrite_mem;
114 uint64_t condition_val64;
115 uint32_t condition_val32;
116
117 int offset = tags->extractBlkOffset(pkt->getAddr());
118 uint8_t *blk_data = blk->data + offset;
119
120 assert(sizeof(uint64_t) >= pkt->getSize());
121
122 overwrite_mem = true;
123 // keep a copy of our possible write value, and copy what is at the
124 // memory address into the packet
125 pkt->writeData((uint8_t *)&overwrite_val);
126 pkt->setData(blk_data);
127
128 if (pkt->req->isCondSwap()) {
129 if (pkt->getSize() == sizeof(uint64_t)) {
130 condition_val64 = pkt->req->getExtraData();
131 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
132 sizeof(uint64_t));
133 } else if (pkt->getSize() == sizeof(uint32_t)) {
134 condition_val32 = (uint32_t)pkt->req->getExtraData();
135 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
136 sizeof(uint32_t));
137 } else
138 panic("Invalid size for conditional read/write\n");
139 }
140
141 if (overwrite_mem) {
142 std::memcpy(blk_data, &overwrite_val, pkt->getSize());
143 blk->status |= BlkDirty;
144 }
145}
146
147
148void
149Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
150 bool deferred_response, bool pending_downgrade)
151{
152 assert(pkt->isRequest());
153
154 assert(blk && blk->isValid());
155 // Occasionally this is not true... if we are a lower-level cache
156 // satisfying a string of Read and ReadEx requests from
157 // upper-level caches, a Read will mark the block as shared but we
158 // can satisfy a following ReadEx anyway since we can rely on the
159 // Read requester(s) to have buffered the ReadEx snoop and to
160 // invalidate their blocks after receiving them.
161 // assert(!pkt->needsWritable() || blk->isWritable());
162 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
163
164 // Check RMW operations first since both isRead() and
165 // isWrite() will be true for them
166 if (pkt->cmd == MemCmd::SwapReq) {
167 cmpAndSwap(blk, pkt);
168 } else if (pkt->isWrite()) {
169 // we have the block in a writable state and can go ahead,
170 // note that the line may be also be considered writable in
171 // downstream caches along the path to memory, but always
172 // Exclusive, and never Modified
173 assert(blk->isWritable());
174 // Write or WriteLine at the first cache with block in writable state
175 if (blk->checkWrite(pkt)) {
176 pkt->writeDataToBlock(blk->data, blkSize);
177 }
178 // Always mark the line as dirty (and thus transition to the
179 // Modified state) even if we are a failed StoreCond so we
180 // supply data to any snoops that have appended themselves to
181 // this cache before knowing the store will fail.
182 blk->status |= BlkDirty;
183 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (write)\n",
184 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
185 } else if (pkt->isRead()) {
186 if (pkt->isLLSC()) {
187 blk->trackLoadLocked(pkt);
188 }
189
190 // all read responses have a data payload
191 assert(pkt->hasRespData());
192 pkt->setDataFromBlock(blk->data, blkSize);
193
194 // determine if this read is from a (coherent) cache, or not
195 // by looking at the command type; we could potentially add a
196 // packet attribute such as 'FromCache' to make this check a
197 // bit cleaner
198 if (pkt->cmd == MemCmd::ReadExReq ||
199 pkt->cmd == MemCmd::ReadSharedReq ||
200 pkt->cmd == MemCmd::ReadCleanReq ||
201 pkt->cmd == MemCmd::SCUpgradeFailReq) {
202 assert(pkt->getSize() == blkSize);
203 // special handling for coherent block requests from
204 // upper-level caches
205 if (pkt->needsWritable()) {
206 // sanity check
207 assert(pkt->cmd == MemCmd::ReadExReq ||
208 pkt->cmd == MemCmd::SCUpgradeFailReq);
209
210 // if we have a dirty copy, make sure the recipient
211 // keeps it marked dirty (in the modified state)
212 if (blk->isDirty()) {
213 pkt->setCacheResponding();
214 }
215 // on ReadExReq we give up our copy unconditionally,
216 // even if this cache is mostly inclusive, we may want
217 // to revisit this
218 invalidateBlock(blk);
219 } else if (blk->isWritable() && !pending_downgrade &&
220 !pkt->hasSharers() &&
221 pkt->cmd != MemCmd::ReadCleanReq) {
222 // we can give the requester a writable copy on a read
223 // request if:
224 // - we have a writable copy at this level (& below)
225 // - we don't have a pending snoop from below
226 // signaling another read request
227 // - no other cache above has a copy (otherwise it
228 // would have set hasSharers flag when
229 // snooping the packet)
230 // - the read has explicitly asked for a clean
231 // copy of the line
232 if (blk->isDirty()) {
233 // special considerations if we're owner:
234 if (!deferred_response) {
235 // respond with the line in Modified state
236 // (cacheResponding set, hasSharers not set)
237 pkt->setCacheResponding();
238
239 if (clusivity == Enums::mostly_excl) {
240 // if this cache is mostly exclusive with
241 // respect to the cache above, drop the
242 // block, no need to first unset the dirty
243 // bit
244 invalidateBlock(blk);
245 } else {
246 // if this cache is mostly inclusive, we
247 // keep the block in the Exclusive state,
248 // and pass it upwards as Modified
249 // (writable and dirty), hence we have
250 // multiple caches, all on the same path
251 // towards memory, all considering the
252 // same block writable, but only one
253 // considering it Modified
254
255 // we get away with multiple caches (on
256 // the same path to memory) considering
257 // the block writeable as we always enter
258 // the cache hierarchy through a cache,
259 // and first snoop upwards in all other
260 // branches
261 blk->status &= ~BlkDirty;
262 }
263 } else {
264 // if we're responding after our own miss,
265 // there's a window where the recipient didn't
266 // know it was getting ownership and may not
267 // have responded to snoops correctly, so we
268 // have to respond with a shared line
269 pkt->setHasSharers();
270 }
271 }
272 } else {
273 // otherwise only respond with a shared copy
274 pkt->setHasSharers();
275 }
276 }
277 } else {
278 // Upgrade or Invalidate
279 assert(pkt->isUpgrade() || pkt->isInvalidate());
280
281 // for invalidations we could be looking at the temp block
282 // (for upgrades we always allocate)
283 invalidateBlock(blk);
284 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (invalidation)\n",
285 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
286 }
287}
288
289/////////////////////////////////////////////////////
290//
291// Access path: requests coming in from the CPU side
292//
293/////////////////////////////////////////////////////
294
295bool
296Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
297 PacketList &writebacks)
298{
299 // sanity check
300 assert(pkt->isRequest());
301
302 chatty_assert(!(isReadOnly && pkt->isWrite()),
303 "Should never see a write in a read-only cache %s\n",
304 name());
305
306 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__,
307 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
308
309 if (pkt->req->isUncacheable()) {
310 DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(),
311 pkt->req->isInstFetch() ? " (ifetch)" : "",
312 pkt->getAddr());
313
314 // flush and invalidate any existing block
315 CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure()));
316 if (old_blk && old_blk->isValid()) {
317 if (old_blk->isDirty() || writebackClean)
318 writebacks.push_back(writebackBlk(old_blk));
319 else
320 writebacks.push_back(cleanEvictBlk(old_blk));
321 tags->invalidate(old_blk);
322 old_blk->invalidate();
323 }
324
| 1/*
2 * Copyright (c) 2010-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 * Nathan Binkert
44 * Steve Reinhardt
45 * Ron Dreslinski
46 * Andreas Sandberg
47 */
48
49/**
50 * @file
51 * Cache definitions.
52 */
53
54#include "mem/cache/cache.hh"
55
56#include "base/misc.hh"
57#include "base/types.hh"
58#include "debug/Cache.hh"
59#include "debug/CachePort.hh"
60#include "debug/CacheTags.hh"
61#include "debug/CacheVerbose.hh"
62#include "mem/cache/blk.hh"
63#include "mem/cache/mshr.hh"
64#include "mem/cache/prefetch/base.hh"
65#include "sim/sim_exit.hh"
66
67Cache::Cache(const CacheParams *p)
68 : BaseCache(p, p->system->cacheLineSize()),
69 tags(p->tags),
70 prefetcher(p->prefetcher),
71 doFastWrites(true),
72 prefetchOnAccess(p->prefetch_on_access),
73 clusivity(p->clusivity),
74 writebackClean(p->writeback_clean),
75 tempBlockWriteback(nullptr),
76 writebackTempBlockAtomicEvent(this, false,
77 EventBase::Delayed_Writeback_Pri)
78{
79 tempBlock = new CacheBlk();
80 tempBlock->data = new uint8_t[blkSize];
81
82 cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
83 "CpuSidePort");
84 memSidePort = new MemSidePort(p->name + ".mem_side", this,
85 "MemSidePort");
86
87 tags->setCache(this);
88 if (prefetcher)
89 prefetcher->setCache(this);
90}
91
92Cache::~Cache()
93{
94 delete [] tempBlock->data;
95 delete tempBlock;
96
97 delete cpuSidePort;
98 delete memSidePort;
99}
100
101void
102Cache::regStats()
103{
104 BaseCache::regStats();
105}
106
107void
108Cache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
109{
110 assert(pkt->isRequest());
111
112 uint64_t overwrite_val;
113 bool overwrite_mem;
114 uint64_t condition_val64;
115 uint32_t condition_val32;
116
117 int offset = tags->extractBlkOffset(pkt->getAddr());
118 uint8_t *blk_data = blk->data + offset;
119
120 assert(sizeof(uint64_t) >= pkt->getSize());
121
122 overwrite_mem = true;
123 // keep a copy of our possible write value, and copy what is at the
124 // memory address into the packet
125 pkt->writeData((uint8_t *)&overwrite_val);
126 pkt->setData(blk_data);
127
128 if (pkt->req->isCondSwap()) {
129 if (pkt->getSize() == sizeof(uint64_t)) {
130 condition_val64 = pkt->req->getExtraData();
131 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
132 sizeof(uint64_t));
133 } else if (pkt->getSize() == sizeof(uint32_t)) {
134 condition_val32 = (uint32_t)pkt->req->getExtraData();
135 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
136 sizeof(uint32_t));
137 } else
138 panic("Invalid size for conditional read/write\n");
139 }
140
141 if (overwrite_mem) {
142 std::memcpy(blk_data, &overwrite_val, pkt->getSize());
143 blk->status |= BlkDirty;
144 }
145}
146
147
148void
149Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
150 bool deferred_response, bool pending_downgrade)
151{
152 assert(pkt->isRequest());
153
154 assert(blk && blk->isValid());
155 // Occasionally this is not true... if we are a lower-level cache
156 // satisfying a string of Read and ReadEx requests from
157 // upper-level caches, a Read will mark the block as shared but we
158 // can satisfy a following ReadEx anyway since we can rely on the
159 // Read requester(s) to have buffered the ReadEx snoop and to
160 // invalidate their blocks after receiving them.
161 // assert(!pkt->needsWritable() || blk->isWritable());
162 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
163
164 // Check RMW operations first since both isRead() and
165 // isWrite() will be true for them
166 if (pkt->cmd == MemCmd::SwapReq) {
167 cmpAndSwap(blk, pkt);
168 } else if (pkt->isWrite()) {
169 // we have the block in a writable state and can go ahead,
170 // note that the line may be also be considered writable in
171 // downstream caches along the path to memory, but always
172 // Exclusive, and never Modified
173 assert(blk->isWritable());
174 // Write or WriteLine at the first cache with block in writable state
175 if (blk->checkWrite(pkt)) {
176 pkt->writeDataToBlock(blk->data, blkSize);
177 }
178 // Always mark the line as dirty (and thus transition to the
179 // Modified state) even if we are a failed StoreCond so we
180 // supply data to any snoops that have appended themselves to
181 // this cache before knowing the store will fail.
182 blk->status |= BlkDirty;
183 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (write)\n",
184 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
185 } else if (pkt->isRead()) {
186 if (pkt->isLLSC()) {
187 blk->trackLoadLocked(pkt);
188 }
189
190 // all read responses have a data payload
191 assert(pkt->hasRespData());
192 pkt->setDataFromBlock(blk->data, blkSize);
193
194 // determine if this read is from a (coherent) cache, or not
195 // by looking at the command type; we could potentially add a
196 // packet attribute such as 'FromCache' to make this check a
197 // bit cleaner
198 if (pkt->cmd == MemCmd::ReadExReq ||
199 pkt->cmd == MemCmd::ReadSharedReq ||
200 pkt->cmd == MemCmd::ReadCleanReq ||
201 pkt->cmd == MemCmd::SCUpgradeFailReq) {
202 assert(pkt->getSize() == blkSize);
203 // special handling for coherent block requests from
204 // upper-level caches
205 if (pkt->needsWritable()) {
206 // sanity check
207 assert(pkt->cmd == MemCmd::ReadExReq ||
208 pkt->cmd == MemCmd::SCUpgradeFailReq);
209
210 // if we have a dirty copy, make sure the recipient
211 // keeps it marked dirty (in the modified state)
212 if (blk->isDirty()) {
213 pkt->setCacheResponding();
214 }
215 // on ReadExReq we give up our copy unconditionally,
216 // even if this cache is mostly inclusive, we may want
217 // to revisit this
218 invalidateBlock(blk);
219 } else if (blk->isWritable() && !pending_downgrade &&
220 !pkt->hasSharers() &&
221 pkt->cmd != MemCmd::ReadCleanReq) {
222 // we can give the requester a writable copy on a read
223 // request if:
224 // - we have a writable copy at this level (& below)
225 // - we don't have a pending snoop from below
226 // signaling another read request
227 // - no other cache above has a copy (otherwise it
228 // would have set hasSharers flag when
229 // snooping the packet)
230 // - the read has explicitly asked for a clean
231 // copy of the line
232 if (blk->isDirty()) {
233 // special considerations if we're owner:
234 if (!deferred_response) {
235 // respond with the line in Modified state
236 // (cacheResponding set, hasSharers not set)
237 pkt->setCacheResponding();
238
239 if (clusivity == Enums::mostly_excl) {
240 // if this cache is mostly exclusive with
241 // respect to the cache above, drop the
242 // block, no need to first unset the dirty
243 // bit
244 invalidateBlock(blk);
245 } else {
246 // if this cache is mostly inclusive, we
247 // keep the block in the Exclusive state,
248 // and pass it upwards as Modified
249 // (writable and dirty), hence we have
250 // multiple caches, all on the same path
251 // towards memory, all considering the
252 // same block writable, but only one
253 // considering it Modified
254
255 // we get away with multiple caches (on
256 // the same path to memory) considering
257 // the block writeable as we always enter
258 // the cache hierarchy through a cache,
259 // and first snoop upwards in all other
260 // branches
261 blk->status &= ~BlkDirty;
262 }
263 } else {
264 // if we're responding after our own miss,
265 // there's a window where the recipient didn't
266 // know it was getting ownership and may not
267 // have responded to snoops correctly, so we
268 // have to respond with a shared line
269 pkt->setHasSharers();
270 }
271 }
272 } else {
273 // otherwise only respond with a shared copy
274 pkt->setHasSharers();
275 }
276 }
277 } else {
278 // Upgrade or Invalidate
279 assert(pkt->isUpgrade() || pkt->isInvalidate());
280
281 // for invalidations we could be looking at the temp block
282 // (for upgrades we always allocate)
283 invalidateBlock(blk);
284 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (invalidation)\n",
285 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
286 }
287}
288
289/////////////////////////////////////////////////////
290//
291// Access path: requests coming in from the CPU side
292//
293/////////////////////////////////////////////////////
294
295bool
296Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
297 PacketList &writebacks)
298{
299 // sanity check
300 assert(pkt->isRequest());
301
302 chatty_assert(!(isReadOnly && pkt->isWrite()),
303 "Should never see a write in a read-only cache %s\n",
304 name());
305
306 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__,
307 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
308
309 if (pkt->req->isUncacheable()) {
310 DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(),
311 pkt->req->isInstFetch() ? " (ifetch)" : "",
312 pkt->getAddr());
313
314 // flush and invalidate any existing block
315 CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure()));
316 if (old_blk && old_blk->isValid()) {
317 if (old_blk->isDirty() || writebackClean)
318 writebacks.push_back(writebackBlk(old_blk));
319 else
320 writebacks.push_back(cleanEvictBlk(old_blk));
321 tags->invalidate(old_blk);
322 old_blk->invalidate();
323 }
324
|
325 blk = NULL;
| 325 blk = nullptr;
|
326 // lookupLatency is the latency in case the request is uncacheable.
327 lat = lookupLatency;
328 return false;
329 }
330
331 ContextID id = pkt->req->hasContextId() ?
332 pkt->req->contextId() : InvalidContextID;
333 // Here lat is the value passed as parameter to accessBlock() function
334 // that can modify its value.
335 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id);
336
337 DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(),
338 pkt->req->isInstFetch() ? " (ifetch)" : "",
339 pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns",
340 blk ? "hit " + blk->print() : "miss");
341
342
343 if (pkt->isEviction()) {
344 // We check for presence of block in above caches before issuing
345 // Writeback or CleanEvict to write buffer. Therefore the only
346 // possible cases can be of a CleanEvict packet coming from above
347 // encountering a Writeback generated in this cache peer cache and
348 // waiting in the write buffer. Cases of upper level peer caches
349 // generating CleanEvict and Writeback or simply CleanEvict and
350 // CleanEvict almost simultaneously will be caught by snoops sent out
351 // by crossbar.
352 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
353 pkt->isSecure());
354 if (wb_entry) {
355 assert(wb_entry->getNumTargets() == 1);
356 PacketPtr wbPkt = wb_entry->getTarget()->pkt;
357 assert(wbPkt->isWriteback());
358
359 if (pkt->isCleanEviction()) {
360 // The CleanEvict and WritebackClean snoops into other
361 // peer caches of the same level while traversing the
362 // crossbar. If a copy of the block is found, the
363 // packet is deleted in the crossbar. Hence, none of
364 // the other upper level caches connected to this
365 // cache have the block, so we can clear the
366 // BLOCK_CACHED flag in the Writeback if set and
367 // discard the CleanEvict by returning true.
368 wbPkt->clearBlockCached();
369 return true;
370 } else {
371 assert(pkt->cmd == MemCmd::WritebackDirty);
372 // Dirty writeback from above trumps our clean
373 // writeback... discard here
374 // Note: markInService will remove entry from writeback buffer.
375 markInService(wb_entry);
376 delete wbPkt;
377 }
378 }
379 }
380
381 // Writeback handling is special case. We can write the block into
382 // the cache without having a writeable copy (or any copy at all).
383 if (pkt->isWriteback()) {
384 assert(blkSize == pkt->getSize());
385
386 // we could get a clean writeback while we are having
387 // outstanding accesses to a block, do the simple thing for
388 // now and drop the clean writeback so that we do not upset
389 // any ordering/decisions about ownership already taken
390 if (pkt->cmd == MemCmd::WritebackClean &&
391 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
392 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
393 "dropping\n", pkt->getAddr());
394 return true;
395 }
396
| 326 // lookupLatency is the latency in case the request is uncacheable.
327 lat = lookupLatency;
328 return false;
329 }
330
331 ContextID id = pkt->req->hasContextId() ?
332 pkt->req->contextId() : InvalidContextID;
333 // Here lat is the value passed as parameter to accessBlock() function
334 // that can modify its value.
335 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id);
336
337 DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(),
338 pkt->req->isInstFetch() ? " (ifetch)" : "",
339 pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns",
340 blk ? "hit " + blk->print() : "miss");
341
342
343 if (pkt->isEviction()) {
344 // We check for presence of block in above caches before issuing
345 // Writeback or CleanEvict to write buffer. Therefore the only
346 // possible cases can be of a CleanEvict packet coming from above
347 // encountering a Writeback generated in this cache peer cache and
348 // waiting in the write buffer. Cases of upper level peer caches
349 // generating CleanEvict and Writeback or simply CleanEvict and
350 // CleanEvict almost simultaneously will be caught by snoops sent out
351 // by crossbar.
352 WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
353 pkt->isSecure());
354 if (wb_entry) {
355 assert(wb_entry->getNumTargets() == 1);
356 PacketPtr wbPkt = wb_entry->getTarget()->pkt;
357 assert(wbPkt->isWriteback());
358
359 if (pkt->isCleanEviction()) {
360 // The CleanEvict and WritebackClean snoops into other
361 // peer caches of the same level while traversing the
362 // crossbar. If a copy of the block is found, the
363 // packet is deleted in the crossbar. Hence, none of
364 // the other upper level caches connected to this
365 // cache have the block, so we can clear the
366 // BLOCK_CACHED flag in the Writeback if set and
367 // discard the CleanEvict by returning true.
368 wbPkt->clearBlockCached();
369 return true;
370 } else {
371 assert(pkt->cmd == MemCmd::WritebackDirty);
372 // Dirty writeback from above trumps our clean
373 // writeback... discard here
374 // Note: markInService will remove entry from writeback buffer.
375 markInService(wb_entry);
376 delete wbPkt;
377 }
378 }
379 }
380
381 // Writeback handling is special case. We can write the block into
382 // the cache without having a writeable copy (or any copy at all).
383 if (pkt->isWriteback()) {
384 assert(blkSize == pkt->getSize());
385
386 // we could get a clean writeback while we are having
387 // outstanding accesses to a block, do the simple thing for
388 // now and drop the clean writeback so that we do not upset
389 // any ordering/decisions about ownership already taken
390 if (pkt->cmd == MemCmd::WritebackClean &&
391 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
392 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
393 "dropping\n", pkt->getAddr());
394 return true;
395 }
396
|
397 if (blk == NULL) {
| 397 if (blk == nullptr) {
|
398 // need to do a replacement
399 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
| 398 // need to do a replacement
399 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
|
400 if (blk == NULL) {
| 400 if (blk == nullptr) {
|
401 // no replaceable block available: give up, fwd to next level.
402 incMissCount(pkt);
403 return false;
404 }
405 tags->insertBlock(pkt, blk);
406
407 blk->status = (BlkValid | BlkReadable);
408 if (pkt->isSecure()) {
409 blk->status |= BlkSecure;
410 }
411 }
412 // only mark the block dirty if we got a writeback command,
413 // and leave it as is for a clean writeback
414 if (pkt->cmd == MemCmd::WritebackDirty) {
415 blk->status |= BlkDirty;
416 }
417 // if the packet does not have sharers, it is passing
418 // writable, and we got the writeback in Modified or Exclusive
419 // state, if not we are in the Owned or Shared state
420 if (!pkt->hasSharers()) {
421 blk->status |= BlkWritable;
422 }
423 // nothing else to do; writeback doesn't expect response
424 assert(!pkt->needsResponse());
425 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize);
426 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
427 incHitCount(pkt);
428 return true;
429 } else if (pkt->cmd == MemCmd::CleanEvict) {
| 401 // no replaceable block available: give up, fwd to next level.
402 incMissCount(pkt);
403 return false;
404 }
405 tags->insertBlock(pkt, blk);
406
407 blk->status = (BlkValid | BlkReadable);
408 if (pkt->isSecure()) {
409 blk->status |= BlkSecure;
410 }
411 }
412 // only mark the block dirty if we got a writeback command,
413 // and leave it as is for a clean writeback
414 if (pkt->cmd == MemCmd::WritebackDirty) {
415 blk->status |= BlkDirty;
416 }
417 // if the packet does not have sharers, it is passing
418 // writable, and we got the writeback in Modified or Exclusive
419 // state, if not we are in the Owned or Shared state
420 if (!pkt->hasSharers()) {
421 blk->status |= BlkWritable;
422 }
423 // nothing else to do; writeback doesn't expect response
424 assert(!pkt->needsResponse());
425 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize);
426 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
427 incHitCount(pkt);
428 return true;
429 } else if (pkt->cmd == MemCmd::CleanEvict) {
|
430 if (blk != NULL) {
| 430 if (blk != nullptr) {
|
431 // Found the block in the tags, need to stop CleanEvict from
432 // propagating further down the hierarchy. Returning true will
433 // treat the CleanEvict like a satisfied write request and delete
434 // it.
435 return true;
436 }
437 // We didn't find the block here, propagate the CleanEvict further
438 // down the memory hierarchy. Returning false will treat the CleanEvict
439 // like a Writeback which could not find a replaceable block so has to
440 // go to next level.
441 return false;
| 431 // Found the block in the tags, need to stop CleanEvict from
432 // propagating further down the hierarchy. Returning true will
433 // treat the CleanEvict like a satisfied write request and delete
434 // it.
435 return true;
436 }
437 // We didn't find the block here, propagate the CleanEvict further
438 // down the memory hierarchy. Returning false will treat the CleanEvict
439 // like a Writeback which could not find a replaceable block so has to
440 // go to next level.
441 return false;
|
442 } else if ((blk != NULL) &&
| 442 } else if ((blk != nullptr) &&
|
443 (pkt->needsWritable() ? blk->isWritable() :
444 blk->isReadable())) {
445 // OK to satisfy access
446 incHitCount(pkt);
447 satisfyCpuSideRequest(pkt, blk);
448 return true;
449 }
450
| 443 (pkt->needsWritable() ? blk->isWritable() :
444 blk->isReadable())) {
445 // OK to satisfy access
446 incHitCount(pkt);
447 satisfyCpuSideRequest(pkt, blk);
448 return true;
449 }
450
|
451 // Can't satisfy access normally... either no block (blk == NULL)
| 451 // Can't satisfy access normally... either no block (blk == nullptr)
|
452 // or have block but need writable
453
454 incMissCount(pkt);
455
| 452 // or have block but need writable
453
454 incMissCount(pkt);
455
|
456 if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
| 456 if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) {
|
457 // complete miss on store conditional... just give up now
458 pkt->req->setExtraData(0);
459 return true;
460 }
461
462 return false;
463}
464
465void
466Cache::doWritebacks(PacketList& writebacks, Tick forward_time)
467{
468 while (!writebacks.empty()) {
469 PacketPtr wbPkt = writebacks.front();
470 // We use forwardLatency here because we are copying writebacks to
471 // write buffer. Call isCachedAbove for both Writebacks and
472 // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag
473 // in Writebacks and discard CleanEvicts.
474 if (isCachedAbove(wbPkt)) {
475 if (wbPkt->cmd == MemCmd::CleanEvict) {
476 // Delete CleanEvict because cached copies exist above. The
477 // packet destructor will delete the request object because
478 // this is a non-snoop request packet which does not require a
479 // response.
480 delete wbPkt;
481 } else if (wbPkt->cmd == MemCmd::WritebackClean) {
482 // clean writeback, do not send since the block is
483 // still cached above
484 assert(writebackClean);
485 delete wbPkt;
486 } else {
487 assert(wbPkt->cmd == MemCmd::WritebackDirty);
488 // Set BLOCK_CACHED flag in Writeback and send below, so that
489 // the Writeback does not reset the bit corresponding to this
490 // address in the snoop filter below.
491 wbPkt->setBlockCached();
492 allocateWriteBuffer(wbPkt, forward_time);
493 }
494 } else {
495 // If the block is not cached above, send packet below. Both
496 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
497 // reset the bit corresponding to this address in the snoop filter
498 // below.
499 allocateWriteBuffer(wbPkt, forward_time);
500 }
501 writebacks.pop_front();
502 }
503}
504
505void
506Cache::doWritebacksAtomic(PacketList& writebacks)
507{
508 while (!writebacks.empty()) {
509 PacketPtr wbPkt = writebacks.front();
510 // Call isCachedAbove for both Writebacks and CleanEvicts. If
511 // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks
512 // and discard CleanEvicts.
513 if (isCachedAbove(wbPkt, false)) {
514 if (wbPkt->cmd == MemCmd::WritebackDirty) {
515 // Set BLOCK_CACHED flag in Writeback and send below,
516 // so that the Writeback does not reset the bit
517 // corresponding to this address in the snoop filter
518 // below. We can discard CleanEvicts because cached
519 // copies exist above. Atomic mode isCachedAbove
520 // modifies packet to set BLOCK_CACHED flag
521 memSidePort->sendAtomic(wbPkt);
522 }
523 } else {
524 // If the block is not cached above, send packet below. Both
525 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
526 // reset the bit corresponding to this address in the snoop filter
527 // below.
528 memSidePort->sendAtomic(wbPkt);
529 }
530 writebacks.pop_front();
531 // In case of CleanEvicts, the packet destructor will delete the
532 // request object because this is a non-snoop request packet which
533 // does not require a response.
534 delete wbPkt;
535 }
536}
537
538
539void
540Cache::recvTimingSnoopResp(PacketPtr pkt)
541{
542 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
543 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
544
545 assert(pkt->isResponse());
546 assert(!system->bypassCaches());
547
548 // determine if the response is from a snoop request we created
549 // (in which case it should be in the outstandingSnoop), or if we
550 // merely forwarded someone else's snoop request
551 const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) ==
552 outstandingSnoop.end();
553
554 if (!forwardAsSnoop) {
555 // the packet came from this cache, so sink it here and do not
556 // forward it
557 assert(pkt->cmd == MemCmd::HardPFResp);
558
559 outstandingSnoop.erase(pkt->req);
560
561 DPRINTF(Cache, "Got prefetch response from above for addr "
562 "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
563 recvTimingResp(pkt);
564 return;
565 }
566
567 // forwardLatency is set here because there is a response from an
568 // upper level cache.
569 // To pay the delay that occurs if the packet comes from the bus,
570 // we charge also headerDelay.
571 Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay;
572 // Reset the timing of the packet.
573 pkt->headerDelay = pkt->payloadDelay = 0;
574 memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time);
575}
576
577void
578Cache::promoteWholeLineWrites(PacketPtr pkt)
579{
580 // Cache line clearing instructions
581 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
582 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
583 pkt->cmd = MemCmd::WriteLineReq;
584 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
585 }
586}
587
588bool
589Cache::recvTimingReq(PacketPtr pkt)
590{
591 DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print());
592
593 assert(pkt->isRequest());
594
595 // Just forward the packet if caches are disabled.
596 if (system->bypassCaches()) {
597 // @todo This should really enqueue the packet rather
598 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
599 assert(success);
600 return true;
601 }
602
603 promoteWholeLineWrites(pkt);
604
605 if (pkt->cacheResponding()) {
606 // a cache above us (but not where the packet came from) is
607 // responding to the request, in other words it has the line
608 // in Modified or Owned state
609 DPRINTF(Cache, "Cache above responding to %#llx (%s): "
610 "not responding\n",
611 pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
612
613 // if the packet needs the block to be writable, and the cache
614 // that has promised to respond (setting the cache responding
615 // flag) is not providing writable (it is in Owned rather than
616 // the Modified state), we know that there may be other Shared
617 // copies in the system; go out and invalidate them all
618 assert(pkt->needsWritable() && !pkt->responderHadWritable());
619
620 // an upstream cache that had the line in Owned state
621 // (dirty, but not writable), is responding and thus
622 // transferring the dirty line from one branch of the
623 // cache hierarchy to another
624
625 // send out an express snoop and invalidate all other
626 // copies (snooping a packet that needs writable is the
627 // same as an invalidation), thus turning the Owned line
628 // into a Modified line, note that we don't invalidate the
629 // block in the current cache or any other cache on the
630 // path to memory
631
632 // create a downstream express snoop with cleared packet
633 // flags, there is no need to allocate any data as the
634 // packet is merely used to co-ordinate state transitions
635 Packet *snoop_pkt = new Packet(pkt, true, false);
636
637 // also reset the bus time that the original packet has
638 // not yet paid for
639 snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0;
640
641 // make this an instantaneous express snoop, and let the
642 // other caches in the system know that the another cache
643 // is responding, because we have found the authorative
644 // copy (Modified or Owned) that will supply the right
645 // data
646 snoop_pkt->setExpressSnoop();
647 snoop_pkt->setCacheResponding();
648
649 // this express snoop travels towards the memory, and at
650 // every crossbar it is snooped upwards thus reaching
651 // every cache in the system
652 bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt);
653 // express snoops always succeed
654 assert(success);
655
656 // main memory will delete the snoop packet
657
658 // queue for deletion, as opposed to immediate deletion, as
659 // the sending cache is still relying on the packet
660 pendingDelete.reset(pkt);
661
662 // no need to take any further action in this particular cache
663 // as an upstram cache has already committed to responding,
664 // and we have already sent out any express snoops in the
665 // section above to ensure all other copies in the system are
666 // invalidated
667 return true;
668 }
669
670 // anything that is merely forwarded pays for the forward latency and
671 // the delay provided by the crossbar
672 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
673
674 // We use lookupLatency here because it is used to specify the latency
675 // to access.
676 Cycles lat = lookupLatency;
| 457 // complete miss on store conditional... just give up now
458 pkt->req->setExtraData(0);
459 return true;
460 }
461
462 return false;
463}
464
465void
466Cache::doWritebacks(PacketList& writebacks, Tick forward_time)
467{
468 while (!writebacks.empty()) {
469 PacketPtr wbPkt = writebacks.front();
470 // We use forwardLatency here because we are copying writebacks to
471 // write buffer. Call isCachedAbove for both Writebacks and
472 // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag
473 // in Writebacks and discard CleanEvicts.
474 if (isCachedAbove(wbPkt)) {
475 if (wbPkt->cmd == MemCmd::CleanEvict) {
476 // Delete CleanEvict because cached copies exist above. The
477 // packet destructor will delete the request object because
478 // this is a non-snoop request packet which does not require a
479 // response.
480 delete wbPkt;
481 } else if (wbPkt->cmd == MemCmd::WritebackClean) {
482 // clean writeback, do not send since the block is
483 // still cached above
484 assert(writebackClean);
485 delete wbPkt;
486 } else {
487 assert(wbPkt->cmd == MemCmd::WritebackDirty);
488 // Set BLOCK_CACHED flag in Writeback and send below, so that
489 // the Writeback does not reset the bit corresponding to this
490 // address in the snoop filter below.
491 wbPkt->setBlockCached();
492 allocateWriteBuffer(wbPkt, forward_time);
493 }
494 } else {
495 // If the block is not cached above, send packet below. Both
496 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
497 // reset the bit corresponding to this address in the snoop filter
498 // below.
499 allocateWriteBuffer(wbPkt, forward_time);
500 }
501 writebacks.pop_front();
502 }
503}
504
505void
506Cache::doWritebacksAtomic(PacketList& writebacks)
507{
508 while (!writebacks.empty()) {
509 PacketPtr wbPkt = writebacks.front();
510 // Call isCachedAbove for both Writebacks and CleanEvicts. If
511 // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks
512 // and discard CleanEvicts.
513 if (isCachedAbove(wbPkt, false)) {
514 if (wbPkt->cmd == MemCmd::WritebackDirty) {
515 // Set BLOCK_CACHED flag in Writeback and send below,
516 // so that the Writeback does not reset the bit
517 // corresponding to this address in the snoop filter
518 // below. We can discard CleanEvicts because cached
519 // copies exist above. Atomic mode isCachedAbove
520 // modifies packet to set BLOCK_CACHED flag
521 memSidePort->sendAtomic(wbPkt);
522 }
523 } else {
524 // If the block is not cached above, send packet below. Both
525 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
526 // reset the bit corresponding to this address in the snoop filter
527 // below.
528 memSidePort->sendAtomic(wbPkt);
529 }
530 writebacks.pop_front();
531 // In case of CleanEvicts, the packet destructor will delete the
532 // request object because this is a non-snoop request packet which
533 // does not require a response.
534 delete wbPkt;
535 }
536}
537
538
539void
540Cache::recvTimingSnoopResp(PacketPtr pkt)
541{
542 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
543 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
544
545 assert(pkt->isResponse());
546 assert(!system->bypassCaches());
547
548 // determine if the response is from a snoop request we created
549 // (in which case it should be in the outstandingSnoop), or if we
550 // merely forwarded someone else's snoop request
551 const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) ==
552 outstandingSnoop.end();
553
554 if (!forwardAsSnoop) {
555 // the packet came from this cache, so sink it here and do not
556 // forward it
557 assert(pkt->cmd == MemCmd::HardPFResp);
558
559 outstandingSnoop.erase(pkt->req);
560
561 DPRINTF(Cache, "Got prefetch response from above for addr "
562 "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
563 recvTimingResp(pkt);
564 return;
565 }
566
567 // forwardLatency is set here because there is a response from an
568 // upper level cache.
569 // To pay the delay that occurs if the packet comes from the bus,
570 // we charge also headerDelay.
571 Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay;
572 // Reset the timing of the packet.
573 pkt->headerDelay = pkt->payloadDelay = 0;
574 memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time);
575}
576
577void
578Cache::promoteWholeLineWrites(PacketPtr pkt)
579{
580 // Cache line clearing instructions
581 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
582 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
583 pkt->cmd = MemCmd::WriteLineReq;
584 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
585 }
586}
587
588bool
589Cache::recvTimingReq(PacketPtr pkt)
590{
591 DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print());
592
593 assert(pkt->isRequest());
594
595 // Just forward the packet if caches are disabled.
596 if (system->bypassCaches()) {
597 // @todo This should really enqueue the packet rather
598 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
599 assert(success);
600 return true;
601 }
602
603 promoteWholeLineWrites(pkt);
604
605 if (pkt->cacheResponding()) {
606 // a cache above us (but not where the packet came from) is
607 // responding to the request, in other words it has the line
608 // in Modified or Owned state
609 DPRINTF(Cache, "Cache above responding to %#llx (%s): "
610 "not responding\n",
611 pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
612
613 // if the packet needs the block to be writable, and the cache
614 // that has promised to respond (setting the cache responding
615 // flag) is not providing writable (it is in Owned rather than
616 // the Modified state), we know that there may be other Shared
617 // copies in the system; go out and invalidate them all
618 assert(pkt->needsWritable() && !pkt->responderHadWritable());
619
620 // an upstream cache that had the line in Owned state
621 // (dirty, but not writable), is responding and thus
622 // transferring the dirty line from one branch of the
623 // cache hierarchy to another
624
625 // send out an express snoop and invalidate all other
626 // copies (snooping a packet that needs writable is the
627 // same as an invalidation), thus turning the Owned line
628 // into a Modified line, note that we don't invalidate the
629 // block in the current cache or any other cache on the
630 // path to memory
631
632 // create a downstream express snoop with cleared packet
633 // flags, there is no need to allocate any data as the
634 // packet is merely used to co-ordinate state transitions
635 Packet *snoop_pkt = new Packet(pkt, true, false);
636
637 // also reset the bus time that the original packet has
638 // not yet paid for
639 snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0;
640
641 // make this an instantaneous express snoop, and let the
642 // other caches in the system know that the another cache
643 // is responding, because we have found the authorative
644 // copy (Modified or Owned) that will supply the right
645 // data
646 snoop_pkt->setExpressSnoop();
647 snoop_pkt->setCacheResponding();
648
649 // this express snoop travels towards the memory, and at
650 // every crossbar it is snooped upwards thus reaching
651 // every cache in the system
652 bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt);
653 // express snoops always succeed
654 assert(success);
655
656 // main memory will delete the snoop packet
657
658 // queue for deletion, as opposed to immediate deletion, as
659 // the sending cache is still relying on the packet
660 pendingDelete.reset(pkt);
661
662 // no need to take any further action in this particular cache
663 // as an upstram cache has already committed to responding,
664 // and we have already sent out any express snoops in the
665 // section above to ensure all other copies in the system are
666 // invalidated
667 return true;
668 }
669
670 // anything that is merely forwarded pays for the forward latency and
671 // the delay provided by the crossbar
672 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
673
674 // We use lookupLatency here because it is used to specify the latency
675 // to access.
676 Cycles lat = lookupLatency;
|
677 CacheBlk *blk = NULL;
| 677 CacheBlk *blk = nullptr;
|
678 bool satisfied = false;
679 {
680 PacketList writebacks;
681 // Note that lat is passed by reference here. The function
682 // access() calls accessBlock() which can modify lat value.
683 satisfied = access(pkt, blk, lat, writebacks);
684
685 // copy writebacks to write buffer here to ensure they logically
686 // proceed anything happening below
687 doWritebacks(writebacks, forward_time);
688 }
689
690 // Here we charge the headerDelay that takes into account the latencies
691 // of the bus, if the packet comes from it.
692 // The latency charged it is just lat that is the value of lookupLatency
693 // modified by access() function, or if not just lookupLatency.
694 // In case of a hit we are neglecting response latency.
695 // In case of a miss we are neglecting forward latency.
696 Tick request_time = clockEdge(lat) + pkt->headerDelay;
697 // Here we reset the timing of the packet.
698 pkt->headerDelay = pkt->payloadDelay = 0;
699
700 // track time of availability of next prefetch, if any
701 Tick next_pf_time = MaxTick;
702
703 bool needsResponse = pkt->needsResponse();
704
705 if (satisfied) {
706 // should never be satisfying an uncacheable access as we
707 // flush and invalidate any existing block as part of the
708 // lookup
709 assert(!pkt->req->isUncacheable());
710
711 // hit (for all other request types)
712
713 if (prefetcher && (prefetchOnAccess ||
714 (blk && blk->wasPrefetched()))) {
715 if (blk)
716 blk->status &= ~BlkHWPrefetched;
717
718 // Don't notify on SWPrefetch
719 if (!pkt->cmd.isSWPrefetch())
720 next_pf_time = prefetcher->notify(pkt);
721 }
722
723 if (needsResponse) {
724 pkt->makeTimingResponse();
725 // @todo: Make someone pay for this
726 pkt->headerDelay = pkt->payloadDelay = 0;
727
728 // In this case we are considering request_time that takes
729 // into account the delay of the xbar, if any, and just
730 // lat, neglecting responseLatency, modelling hit latency
731 // just as lookupLatency or or the value of lat overriden
732 // by access(), that calls accessBlock() function.
733 cpuSidePort->schedTimingResp(pkt, request_time, true);
734 } else {
735 DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n",
736 __func__, pkt->cmdString(), pkt->getAddr(),
737 pkt->getSize());
738
739 // queue the packet for deletion, as the sending cache is
740 // still relying on it; if the block is found in access(),
741 // CleanEvict and Writeback messages will be deleted
742 // here as well
743 pendingDelete.reset(pkt);
744 }
745 } else {
746 // miss
747
748 Addr blk_addr = blockAlign(pkt->getAddr());
749
750 // ignore any existing MSHR if we are dealing with an
751 // uncacheable request
752 MSHR *mshr = pkt->req->isUncacheable() ? nullptr :
753 mshrQueue.findMatch(blk_addr, pkt->isSecure());
754
755 // Software prefetch handling:
756 // To keep the core from waiting on data it won't look at
757 // anyway, send back a response with dummy data. Miss handling
758 // will continue asynchronously. Unfortunately, the core will
759 // insist upon freeing original Packet/Request, so we have to
760 // create a new pair with a different lifecycle. Note that this
761 // processing happens before any MSHR munging on the behalf of
762 // this request because this new Request will be the one stored
763 // into the MSHRs, not the original.
764 if (pkt->cmd.isSWPrefetch()) {
765 assert(needsResponse);
766 assert(pkt->req->hasPaddr());
767 assert(!pkt->req->isUncacheable());
768
769 // There's no reason to add a prefetch as an additional target
770 // to an existing MSHR. If an outstanding request is already
771 // in progress, there is nothing for the prefetch to do.
772 // If this is the case, we don't even create a request at all.
773 PacketPtr pf = nullptr;
774
775 if (!mshr) {
776 // copy the request and create a new SoftPFReq packet
777 RequestPtr req = new Request(pkt->req->getPaddr(),
778 pkt->req->getSize(),
779 pkt->req->getFlags(),
780 pkt->req->masterId());
781 pf = new Packet(req, pkt->cmd);
782 pf->allocate();
783 assert(pf->getAddr() == pkt->getAddr());
784 assert(pf->getSize() == pkt->getSize());
785 }
786
787 pkt->makeTimingResponse();
788
789 // request_time is used here, taking into account lat and the delay
790 // charged if the packet comes from the xbar.
791 cpuSidePort->schedTimingResp(pkt, request_time, true);
792
793 // If an outstanding request is in progress (we found an
794 // MSHR) this is set to null
795 pkt = pf;
796 }
797
798 if (mshr) {
799 /// MSHR hit
800 /// @note writebacks will be checked in getNextMSHR()
801 /// for any conflicting requests to the same block
802
803 //@todo remove hw_pf here
804
805 // Coalesce unless it was a software prefetch (see above).
806 if (pkt) {
807 assert(!pkt->isWriteback());
808 // CleanEvicts corresponding to blocks which have
809 // outstanding requests in MSHRs are simply sunk here
810 if (pkt->cmd == MemCmd::CleanEvict) {
811 pendingDelete.reset(pkt);
812 } else {
813 DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx "
814 "size %d\n", __func__, pkt->cmdString(),
815 pkt->getAddr(), pkt->getSize());
816
817 assert(pkt->req->masterId() < system->maxMasters());
818 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
819 // We use forward_time here because it is the same
820 // considering new targets. We have multiple
821 // requests for the same address here. It
822 // specifies the latency to allocate an internal
823 // buffer and to schedule an event to the queued
824 // port and also takes into account the additional
825 // delay of the xbar.
826 mshr->allocateTarget(pkt, forward_time, order++,
827 allocOnFill(pkt->cmd));
828 if (mshr->getNumTargets() == numTarget) {
829 noTargetMSHR = mshr;
830 setBlocked(Blocked_NoTargets);
831 // need to be careful with this... if this mshr isn't
832 // ready yet (i.e. time > curTick()), we don't want to
833 // move it ahead of mshrs that are ready
834 // mshrQueue.moveToFront(mshr);
835 }
836 }
837 // We should call the prefetcher reguardless if the request is
838 // satisfied or not, reguardless if the request is in the MSHR
839 // or not. The request could be a ReadReq hit, but still not
840 // satisfied (potentially because of a prior write to the same
841 // cache line. So, even when not satisfied, tehre is an MSHR
842 // already allocated for this, we need to let the prefetcher
843 // know about the request
844 if (prefetcher) {
845 // Don't notify on SWPrefetch
846 if (!pkt->cmd.isSWPrefetch())
847 next_pf_time = prefetcher->notify(pkt);
848 }
849 }
850 } else {
851 // no MSHR
852 assert(pkt->req->masterId() < system->maxMasters());
853 if (pkt->req->isUncacheable()) {
854 mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
855 } else {
856 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
857 }
858
859 if (pkt->isEviction() ||
860 (pkt->req->isUncacheable() && pkt->isWrite())) {
861 // We use forward_time here because there is an
862 // uncached memory write, forwarded to WriteBuffer.
863 allocateWriteBuffer(pkt, forward_time);
864 } else {
865 if (blk && blk->isValid()) {
866 // should have flushed and have no valid block
867 assert(!pkt->req->isUncacheable());
868
869 // If we have a write miss to a valid block, we
870 // need to mark the block non-readable. Otherwise
871 // if we allow reads while there's an outstanding
872 // write miss, the read could return stale data
873 // out of the cache block... a more aggressive
874 // system could detect the overlap (if any) and
875 // forward data out of the MSHRs, but we don't do
876 // that yet. Note that we do need to leave the
877 // block valid so that it stays in the cache, in
878 // case we get an upgrade response (and hence no
879 // new data) when the write miss completes.
880 // As long as CPUs do proper store/load forwarding
881 // internally, and have a sufficiently weak memory
882 // model, this is probably unnecessary, but at some
883 // point it must have seemed like we needed it...
884 assert(pkt->needsWritable());
885 assert(!blk->isWritable());
886 blk->status &= ~BlkReadable;
887 }
888 // Here we are using forward_time, modelling the latency of
889 // a miss (outbound) just as forwardLatency, neglecting the
890 // lookupLatency component.
891 allocateMissBuffer(pkt, forward_time);
892 }
893
894 if (prefetcher) {
895 // Don't notify on SWPrefetch
896 if (!pkt->cmd.isSWPrefetch())
897 next_pf_time = prefetcher->notify(pkt);
898 }
899 }
900 }
901
902 if (next_pf_time != MaxTick)
903 schedMemSideSendEvent(next_pf_time);
904
905 return true;
906}
907
908PacketPtr
909Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
910 bool needsWritable) const
911{
912 // should never see evictions here
913 assert(!cpu_pkt->isEviction());
914
915 bool blkValid = blk && blk->isValid();
916
917 if (cpu_pkt->req->isUncacheable() ||
918 (!blkValid && cpu_pkt->isUpgrade())) {
919 // uncacheable requests and upgrades from upper-level caches
920 // that missed completely just go through as is
921 return nullptr;
922 }
923
924 assert(cpu_pkt->needsResponse());
925
926 MemCmd cmd;
927 // @TODO make useUpgrades a parameter.
928 // Note that ownership protocols require upgrade, otherwise a
929 // write miss on a shared owned block will generate a ReadExcl,
930 // which will clobber the owned copy.
931 const bool useUpgrades = true;
932 if (blkValid && useUpgrades) {
933 // only reason to be here is that blk is read only and we need
934 // it to be writable
935 assert(needsWritable);
936 assert(!blk->isWritable());
937 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
938 } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
939 cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
940 // Even though this SC will fail, we still need to send out the
941 // request and get the data to supply it to other snoopers in the case
942 // where the determination the StoreCond fails is delayed due to
943 // all caches not being on the same local bus.
944 cmd = MemCmd::SCUpgradeFailReq;
945 } else if (cpu_pkt->cmd == MemCmd::WriteLineReq ||
946 cpu_pkt->cmd == MemCmd::InvalidateReq) {
947 // forward as invalidate to all other caches, this gives us
948 // the line in Exclusive state, and invalidates all other
949 // copies
950 cmd = MemCmd::InvalidateReq;
951 } else {
952 // block is invalid
953 cmd = needsWritable ? MemCmd::ReadExReq :
954 (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
955 }
956 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
957
958 // if there are upstream caches that have already marked the
959 // packet as having sharers (not passing writable), pass that info
960 // downstream
961 if (cpu_pkt->hasSharers()) {
962 // note that cpu_pkt may have spent a considerable time in the
963 // MSHR queue and that the information could possibly be out
964 // of date, however, there is no harm in conservatively
965 // assuming the block has sharers
966 pkt->setHasSharers();
967 DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx "
968 "size %d\n",
969 __func__, cpu_pkt->cmdString(), pkt->cmdString(),
970 pkt->getAddr(), pkt->getSize());
971 }
972
973 // the packet should be block aligned
974 assert(pkt->getAddr() == blockAlign(pkt->getAddr()));
975
976 pkt->allocate();
977 DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n",
978 __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(),
979 pkt->getSize());
980 return pkt;
981}
982
983
984Tick
985Cache::recvAtomic(PacketPtr pkt)
986{
987 // We are in atomic mode so we pay just for lookupLatency here.
988 Cycles lat = lookupLatency;
989
990 // Forward the request if the system is in cache bypass mode.
991 if (system->bypassCaches())
992 return ticksToCycles(memSidePort->sendAtomic(pkt));
993
994 promoteWholeLineWrites(pkt);
995
996 // follow the same flow as in recvTimingReq, and check if a cache
997 // above us is responding
998 if (pkt->cacheResponding()) {
999 DPRINTF(Cache, "Cache above responding to %#llx (%s): "
1000 "not responding\n",
1001 pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
1002
1003 // if a cache is responding, and it had the line in Owned
1004 // rather than Modified state, we need to invalidate any
1005 // copies that are not on the same path to memory
1006 assert(pkt->needsWritable() && !pkt->responderHadWritable());
1007 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1008
1009 return lat * clockPeriod();
1010 }
1011
1012 // should assert here that there are no outstanding MSHRs or
1013 // writebacks... that would mean that someone used an atomic
1014 // access in timing mode
1015
| 678 bool satisfied = false;
679 {
680 PacketList writebacks;
681 // Note that lat is passed by reference here. The function
682 // access() calls accessBlock() which can modify lat value.
683 satisfied = access(pkt, blk, lat, writebacks);
684
685 // copy writebacks to write buffer here to ensure they logically
686 // proceed anything happening below
687 doWritebacks(writebacks, forward_time);
688 }
689
690 // Here we charge the headerDelay that takes into account the latencies
691 // of the bus, if the packet comes from it.
692 // The latency charged it is just lat that is the value of lookupLatency
693 // modified by access() function, or if not just lookupLatency.
694 // In case of a hit we are neglecting response latency.
695 // In case of a miss we are neglecting forward latency.
696 Tick request_time = clockEdge(lat) + pkt->headerDelay;
697 // Here we reset the timing of the packet.
698 pkt->headerDelay = pkt->payloadDelay = 0;
699
700 // track time of availability of next prefetch, if any
701 Tick next_pf_time = MaxTick;
702
703 bool needsResponse = pkt->needsResponse();
704
705 if (satisfied) {
706 // should never be satisfying an uncacheable access as we
707 // flush and invalidate any existing block as part of the
708 // lookup
709 assert(!pkt->req->isUncacheable());
710
711 // hit (for all other request types)
712
713 if (prefetcher && (prefetchOnAccess ||
714 (blk && blk->wasPrefetched()))) {
715 if (blk)
716 blk->status &= ~BlkHWPrefetched;
717
718 // Don't notify on SWPrefetch
719 if (!pkt->cmd.isSWPrefetch())
720 next_pf_time = prefetcher->notify(pkt);
721 }
722
723 if (needsResponse) {
724 pkt->makeTimingResponse();
725 // @todo: Make someone pay for this
726 pkt->headerDelay = pkt->payloadDelay = 0;
727
728 // In this case we are considering request_time that takes
729 // into account the delay of the xbar, if any, and just
730 // lat, neglecting responseLatency, modelling hit latency
731 // just as lookupLatency or or the value of lat overriden
732 // by access(), that calls accessBlock() function.
733 cpuSidePort->schedTimingResp(pkt, request_time, true);
734 } else {
735 DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n",
736 __func__, pkt->cmdString(), pkt->getAddr(),
737 pkt->getSize());
738
739 // queue the packet for deletion, as the sending cache is
740 // still relying on it; if the block is found in access(),
741 // CleanEvict and Writeback messages will be deleted
742 // here as well
743 pendingDelete.reset(pkt);
744 }
745 } else {
746 // miss
747
748 Addr blk_addr = blockAlign(pkt->getAddr());
749
750 // ignore any existing MSHR if we are dealing with an
751 // uncacheable request
752 MSHR *mshr = pkt->req->isUncacheable() ? nullptr :
753 mshrQueue.findMatch(blk_addr, pkt->isSecure());
754
755 // Software prefetch handling:
756 // To keep the core from waiting on data it won't look at
757 // anyway, send back a response with dummy data. Miss handling
758 // will continue asynchronously. Unfortunately, the core will
759 // insist upon freeing original Packet/Request, so we have to
760 // create a new pair with a different lifecycle. Note that this
761 // processing happens before any MSHR munging on the behalf of
762 // this request because this new Request will be the one stored
763 // into the MSHRs, not the original.
764 if (pkt->cmd.isSWPrefetch()) {
765 assert(needsResponse);
766 assert(pkt->req->hasPaddr());
767 assert(!pkt->req->isUncacheable());
768
769 // There's no reason to add a prefetch as an additional target
770 // to an existing MSHR. If an outstanding request is already
771 // in progress, there is nothing for the prefetch to do.
772 // If this is the case, we don't even create a request at all.
773 PacketPtr pf = nullptr;
774
775 if (!mshr) {
776 // copy the request and create a new SoftPFReq packet
777 RequestPtr req = new Request(pkt->req->getPaddr(),
778 pkt->req->getSize(),
779 pkt->req->getFlags(),
780 pkt->req->masterId());
781 pf = new Packet(req, pkt->cmd);
782 pf->allocate();
783 assert(pf->getAddr() == pkt->getAddr());
784 assert(pf->getSize() == pkt->getSize());
785 }
786
787 pkt->makeTimingResponse();
788
789 // request_time is used here, taking into account lat and the delay
790 // charged if the packet comes from the xbar.
791 cpuSidePort->schedTimingResp(pkt, request_time, true);
792
793 // If an outstanding request is in progress (we found an
794 // MSHR) this is set to null
795 pkt = pf;
796 }
797
798 if (mshr) {
799 /// MSHR hit
800 /// @note writebacks will be checked in getNextMSHR()
801 /// for any conflicting requests to the same block
802
803 //@todo remove hw_pf here
804
805 // Coalesce unless it was a software prefetch (see above).
806 if (pkt) {
807 assert(!pkt->isWriteback());
808 // CleanEvicts corresponding to blocks which have
809 // outstanding requests in MSHRs are simply sunk here
810 if (pkt->cmd == MemCmd::CleanEvict) {
811 pendingDelete.reset(pkt);
812 } else {
813 DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx "
814 "size %d\n", __func__, pkt->cmdString(),
815 pkt->getAddr(), pkt->getSize());
816
817 assert(pkt->req->masterId() < system->maxMasters());
818 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
819 // We use forward_time here because it is the same
820 // considering new targets. We have multiple
821 // requests for the same address here. It
822 // specifies the latency to allocate an internal
823 // buffer and to schedule an event to the queued
824 // port and also takes into account the additional
825 // delay of the xbar.
826 mshr->allocateTarget(pkt, forward_time, order++,
827 allocOnFill(pkt->cmd));
828 if (mshr->getNumTargets() == numTarget) {
829 noTargetMSHR = mshr;
830 setBlocked(Blocked_NoTargets);
831 // need to be careful with this... if this mshr isn't
832 // ready yet (i.e. time > curTick()), we don't want to
833 // move it ahead of mshrs that are ready
834 // mshrQueue.moveToFront(mshr);
835 }
836 }
837 // We should call the prefetcher reguardless if the request is
838 // satisfied or not, reguardless if the request is in the MSHR
839 // or not. The request could be a ReadReq hit, but still not
840 // satisfied (potentially because of a prior write to the same
841 // cache line. So, even when not satisfied, tehre is an MSHR
842 // already allocated for this, we need to let the prefetcher
843 // know about the request
844 if (prefetcher) {
845 // Don't notify on SWPrefetch
846 if (!pkt->cmd.isSWPrefetch())
847 next_pf_time = prefetcher->notify(pkt);
848 }
849 }
850 } else {
851 // no MSHR
852 assert(pkt->req->masterId() < system->maxMasters());
853 if (pkt->req->isUncacheable()) {
854 mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
855 } else {
856 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
857 }
858
859 if (pkt->isEviction() ||
860 (pkt->req->isUncacheable() && pkt->isWrite())) {
861 // We use forward_time here because there is an
862 // uncached memory write, forwarded to WriteBuffer.
863 allocateWriteBuffer(pkt, forward_time);
864 } else {
865 if (blk && blk->isValid()) {
866 // should have flushed and have no valid block
867 assert(!pkt->req->isUncacheable());
868
869 // If we have a write miss to a valid block, we
870 // need to mark the block non-readable. Otherwise
871 // if we allow reads while there's an outstanding
872 // write miss, the read could return stale data
873 // out of the cache block... a more aggressive
874 // system could detect the overlap (if any) and
875 // forward data out of the MSHRs, but we don't do
876 // that yet. Note that we do need to leave the
877 // block valid so that it stays in the cache, in
878 // case we get an upgrade response (and hence no
879 // new data) when the write miss completes.
880 // As long as CPUs do proper store/load forwarding
881 // internally, and have a sufficiently weak memory
882 // model, this is probably unnecessary, but at some
883 // point it must have seemed like we needed it...
884 assert(pkt->needsWritable());
885 assert(!blk->isWritable());
886 blk->status &= ~BlkReadable;
887 }
888 // Here we are using forward_time, modelling the latency of
889 // a miss (outbound) just as forwardLatency, neglecting the
890 // lookupLatency component.
891 allocateMissBuffer(pkt, forward_time);
892 }
893
894 if (prefetcher) {
895 // Don't notify on SWPrefetch
896 if (!pkt->cmd.isSWPrefetch())
897 next_pf_time = prefetcher->notify(pkt);
898 }
899 }
900 }
901
902 if (next_pf_time != MaxTick)
903 schedMemSideSendEvent(next_pf_time);
904
905 return true;
906}
907
908PacketPtr
909Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
910 bool needsWritable) const
911{
912 // should never see evictions here
913 assert(!cpu_pkt->isEviction());
914
915 bool blkValid = blk && blk->isValid();
916
917 if (cpu_pkt->req->isUncacheable() ||
918 (!blkValid && cpu_pkt->isUpgrade())) {
919 // uncacheable requests and upgrades from upper-level caches
920 // that missed completely just go through as is
921 return nullptr;
922 }
923
924 assert(cpu_pkt->needsResponse());
925
926 MemCmd cmd;
927 // @TODO make useUpgrades a parameter.
928 // Note that ownership protocols require upgrade, otherwise a
929 // write miss on a shared owned block will generate a ReadExcl,
930 // which will clobber the owned copy.
931 const bool useUpgrades = true;
932 if (blkValid && useUpgrades) {
933 // only reason to be here is that blk is read only and we need
934 // it to be writable
935 assert(needsWritable);
936 assert(!blk->isWritable());
937 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
938 } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
939 cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
940 // Even though this SC will fail, we still need to send out the
941 // request and get the data to supply it to other snoopers in the case
942 // where the determination the StoreCond fails is delayed due to
943 // all caches not being on the same local bus.
944 cmd = MemCmd::SCUpgradeFailReq;
945 } else if (cpu_pkt->cmd == MemCmd::WriteLineReq ||
946 cpu_pkt->cmd == MemCmd::InvalidateReq) {
947 // forward as invalidate to all other caches, this gives us
948 // the line in Exclusive state, and invalidates all other
949 // copies
950 cmd = MemCmd::InvalidateReq;
951 } else {
952 // block is invalid
953 cmd = needsWritable ? MemCmd::ReadExReq :
954 (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
955 }
956 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
957
958 // if there are upstream caches that have already marked the
959 // packet as having sharers (not passing writable), pass that info
960 // downstream
961 if (cpu_pkt->hasSharers()) {
962 // note that cpu_pkt may have spent a considerable time in the
963 // MSHR queue and that the information could possibly be out
964 // of date, however, there is no harm in conservatively
965 // assuming the block has sharers
966 pkt->setHasSharers();
967 DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx "
968 "size %d\n",
969 __func__, cpu_pkt->cmdString(), pkt->cmdString(),
970 pkt->getAddr(), pkt->getSize());
971 }
972
973 // the packet should be block aligned
974 assert(pkt->getAddr() == blockAlign(pkt->getAddr()));
975
976 pkt->allocate();
977 DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n",
978 __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(),
979 pkt->getSize());
980 return pkt;
981}
982
983
984Tick
985Cache::recvAtomic(PacketPtr pkt)
986{
987 // We are in atomic mode so we pay just for lookupLatency here.
988 Cycles lat = lookupLatency;
989
990 // Forward the request if the system is in cache bypass mode.
991 if (system->bypassCaches())
992 return ticksToCycles(memSidePort->sendAtomic(pkt));
993
994 promoteWholeLineWrites(pkt);
995
996 // follow the same flow as in recvTimingReq, and check if a cache
997 // above us is responding
998 if (pkt->cacheResponding()) {
999 DPRINTF(Cache, "Cache above responding to %#llx (%s): "
1000 "not responding\n",
1001 pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
1002
1003 // if a cache is responding, and it had the line in Owned
1004 // rather than Modified state, we need to invalidate any
1005 // copies that are not on the same path to memory
1006 assert(pkt->needsWritable() && !pkt->responderHadWritable());
1007 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1008
1009 return lat * clockPeriod();
1010 }
1011
1012 // should assert here that there are no outstanding MSHRs or
1013 // writebacks... that would mean that someone used an atomic
1014 // access in timing mode
1015
|
1016 CacheBlk *blk = NULL;
| 1016 CacheBlk *blk = nullptr;
|
1017 PacketList writebacks;
1018 bool satisfied = access(pkt, blk, lat, writebacks);
1019
1020 // handle writebacks resulting from the access here to ensure they
1021 // logically proceed anything happening below
1022 doWritebacksAtomic(writebacks);
1023
1024 if (!satisfied) {
1025 // MISS
1026
1027 // deal with the packets that go through the write path of
1028 // the cache, i.e. any evictions and uncacheable writes
1029 if (pkt->isEviction() ||
1030 (pkt->req->isUncacheable() && pkt->isWrite())) {
1031 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1032 return lat * clockPeriod();
1033 }
1034 // only misses left
1035
1036 PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
1037
| 1017 PacketList writebacks;
1018 bool satisfied = access(pkt, blk, lat, writebacks);
1019
1020 // handle writebacks resulting from the access here to ensure they
1021 // logically proceed anything happening below
1022 doWritebacksAtomic(writebacks);
1023
1024 if (!satisfied) {
1025 // MISS
1026
1027 // deal with the packets that go through the write path of
1028 // the cache, i.e. any evictions and uncacheable writes
1029 if (pkt->isEviction() ||
1030 (pkt->req->isUncacheable() && pkt->isWrite())) {
1031 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1032 return lat * clockPeriod();
1033 }
1034 // only misses left
1035
1036 PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
1037
|
1038 bool is_forward = (bus_pkt == NULL);
| 1038 bool is_forward = (bus_pkt == nullptr);
|
1039
1040 if (is_forward) {
1041 // just forwarding the same request to the next level
1042 // no local cache operation involved
1043 bus_pkt = pkt;
1044 }
1045
1046 DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n",
1047 bus_pkt->cmdString(), bus_pkt->getAddr(),
1048 bus_pkt->isSecure() ? "s" : "ns");
1049
1050#if TRACING_ON
1051 CacheBlk::State old_state = blk ? blk->status : 0;
1052#endif
1053
1054 lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
1055
1056 bool is_invalidate = bus_pkt->isInvalidate();
1057
1058 // We are now dealing with the response handling
1059 DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in "
1060 "state %i\n", bus_pkt->cmdString(), bus_pkt->getAddr(),
1061 bus_pkt->isSecure() ? "s" : "ns",
1062 old_state);
1063
1064 // If packet was a forward, the response (if any) is already
1065 // in place in the bus_pkt == pkt structure, so we don't need
1066 // to do anything. Otherwise, use the separate bus_pkt to
1067 // generate response to pkt and then delete it.
1068 if (!is_forward) {
1069 if (pkt->needsResponse()) {
1070 assert(bus_pkt->isResponse());
1071 if (bus_pkt->isError()) {
1072 pkt->makeAtomicResponse();
1073 pkt->copyError(bus_pkt);
1074 } else if (pkt->cmd == MemCmd::WriteLineReq) {
1075 // note the use of pkt, not bus_pkt here.
1076
1077 // write-line request to the cache that promoted
1078 // the write to a whole line
1079 blk = handleFill(pkt, blk, writebacks,
1080 allocOnFill(pkt->cmd));
1081 assert(blk != NULL);
1082 is_invalidate = false;
1083 satisfyCpuSideRequest(pkt, blk);
1084 } else if (bus_pkt->isRead() ||
1085 bus_pkt->cmd == MemCmd::UpgradeResp) {
1086 // we're updating cache state to allow us to
1087 // satisfy the upstream request from the cache
1088 blk = handleFill(bus_pkt, blk, writebacks,
1089 allocOnFill(pkt->cmd));
1090 satisfyCpuSideRequest(pkt, blk);
1091 } else {
1092 // we're satisfying the upstream request without
1093 // modifying cache state, e.g., a write-through
1094 pkt->makeAtomicResponse();
1095 }
1096 }
1097 delete bus_pkt;
1098 }
1099
1100 if (is_invalidate && blk && blk->isValid()) {
1101 invalidateBlock(blk);
1102 }
1103 }
1104
1105 // Note that we don't invoke the prefetcher at all in atomic mode.
1106 // It's not clear how to do it properly, particularly for
1107 // prefetchers that aggressively generate prefetch candidates and
1108 // rely on bandwidth contention to throttle them; these will tend
1109 // to pollute the cache in atomic mode since there is no bandwidth
1110 // contention. If we ever do want to enable prefetching in atomic
1111 // mode, though, this is the place to do it... see timingAccess()
1112 // for an example (though we'd want to issue the prefetch(es)
1113 // immediately rather than calling requestMemSideBus() as we do
1114 // there).
1115
1116 // do any writebacks resulting from the response handling
1117 doWritebacksAtomic(writebacks);
1118
1119 // if we used temp block, check to see if its valid and if so
1120 // clear it out, but only do so after the call to recvAtomic is
1121 // finished so that any downstream observers (such as a snoop
1122 // filter), first see the fill, and only then see the eviction
1123 if (blk == tempBlock && tempBlock->isValid()) {
1124 // the atomic CPU calls recvAtomic for fetch and load/store
1125 // sequentuially, and we may already have a tempBlock
1126 // writeback from the fetch that we have not yet sent
1127 if (tempBlockWriteback) {
1128 // if that is the case, write the prevoius one back, and
1129 // do not schedule any new event
1130 writebackTempBlockAtomic();
1131 } else {
1132 // the writeback/clean eviction happens after the call to
1133 // recvAtomic has finished (but before any successive
1134 // calls), so that the response handling from the fill is
1135 // allowed to happen first
1136 schedule(writebackTempBlockAtomicEvent, curTick());
1137 }
1138
1139 tempBlockWriteback = (blk->isDirty() || writebackClean) ?
1140 writebackBlk(blk) : cleanEvictBlk(blk);
1141 blk->invalidate();
1142 }
1143
1144 if (pkt->needsResponse()) {
1145 pkt->makeAtomicResponse();
1146 }
1147
1148 return lat * clockPeriod();
1149}
1150
1151
1152void
1153Cache::functionalAccess(PacketPtr pkt, bool fromCpuSide)
1154{
1155 if (system->bypassCaches()) {
1156 // Packets from the memory side are snoop request and
1157 // shouldn't happen in bypass mode.
1158 assert(fromCpuSide);
1159
1160 // The cache should be flushed if we are in cache bypass mode,
1161 // so we don't need to check if we need to update anything.
1162 memSidePort->sendFunctional(pkt);
1163 return;
1164 }
1165
1166 Addr blk_addr = blockAlign(pkt->getAddr());
1167 bool is_secure = pkt->isSecure();
1168 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
1169 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
1170
1171 pkt->pushLabel(name());
1172
1173 CacheBlkPrintWrapper cbpw(blk);
1174
1175 // Note that just because an L2/L3 has valid data doesn't mean an
1176 // L1 doesn't have a more up-to-date modified copy that still
1177 // needs to be found. As a result we always update the request if
1178 // we have it, but only declare it satisfied if we are the owner.
1179
1180 // see if we have data at all (owned or otherwise)
1181 bool have_data = blk && blk->isValid()
1182 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
1183 blk->data);
1184
1185 // data we have is dirty if marked as such or if we have an
1186 // in-service MSHR that is pending a modified line
1187 bool have_dirty =
1188 have_data && (blk->isDirty() ||
1189 (mshr && mshr->inService && mshr->isPendingModified()));
1190
1191 bool done = have_dirty
1192 || cpuSidePort->checkFunctional(pkt)
1193 || mshrQueue.checkFunctional(pkt, blk_addr)
1194 || writeBuffer.checkFunctional(pkt, blk_addr)
1195 || memSidePort->checkFunctional(pkt);
1196
1197 DPRINTF(CacheVerbose, "functional %s %#llx (%s) %s%s%s\n",
1198 pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns",
1199 (blk && blk->isValid()) ? "valid " : "",
1200 have_data ? "data " : "", done ? "done " : "");
1201
1202 // We're leaving the cache, so pop cache->name() label
1203 pkt->popLabel();
1204
1205 if (done) {
1206 pkt->makeResponse();
1207 } else {
1208 // if it came as a request from the CPU side then make sure it
1209 // continues towards the memory side
1210 if (fromCpuSide) {
1211 memSidePort->sendFunctional(pkt);
1212 } else if (forwardSnoops && cpuSidePort->isSnooping()) {
1213 // if it came from the memory side, it must be a snoop request
1214 // and we should only forward it if we are forwarding snoops
1215 cpuSidePort->sendFunctionalSnoop(pkt);
1216 }
1217 }
1218}
1219
1220
1221/////////////////////////////////////////////////////
1222//
1223// Response handling: responses from the memory side
1224//
1225/////////////////////////////////////////////////////
1226
1227
1228void
1229Cache::handleUncacheableWriteResp(PacketPtr pkt)
1230{
1231 Tick completion_time = clockEdge(responseLatency) +
1232 pkt->headerDelay + pkt->payloadDelay;
1233
1234 // Reset the bus additional time as it is now accounted for
1235 pkt->headerDelay = pkt->payloadDelay = 0;
1236
1237 cpuSidePort->schedTimingResp(pkt, completion_time, true);
1238}
1239
1240void
1241Cache::recvTimingResp(PacketPtr pkt)
1242{
1243 assert(pkt->isResponse());
1244
1245 // all header delay should be paid for by the crossbar, unless
1246 // this is a prefetch response from above
1247 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
1248 "%s saw a non-zero packet delay\n", name());
1249
1250 bool is_error = pkt->isError();
1251
1252 if (is_error) {
1253 DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), "
1254 "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns",
1255 pkt->cmdString());
1256 }
1257
1258 DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n",
1259 pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1260 pkt->isSecure() ? "s" : "ns");
1261
1262 // if this is a write, we should be looking at an uncacheable
1263 // write
1264 if (pkt->isWrite()) {
1265 assert(pkt->req->isUncacheable());
1266 handleUncacheableWriteResp(pkt);
1267 return;
1268 }
1269
1270 // we have dealt with any (uncacheable) writes above, from here on
1271 // we know we are dealing with an MSHR due to a miss or a prefetch
1272 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
1273 assert(mshr);
1274
1275 if (mshr == noTargetMSHR) {
1276 // we always clear at least one target
1277 clearBlocked(Blocked_NoTargets);
| 1039
1040 if (is_forward) {
1041 // just forwarding the same request to the next level
1042 // no local cache operation involved
1043 bus_pkt = pkt;
1044 }
1045
1046 DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n",
1047 bus_pkt->cmdString(), bus_pkt->getAddr(),
1048 bus_pkt->isSecure() ? "s" : "ns");
1049
1050#if TRACING_ON
1051 CacheBlk::State old_state = blk ? blk->status : 0;
1052#endif
1053
1054 lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
1055
1056 bool is_invalidate = bus_pkt->isInvalidate();
1057
1058 // We are now dealing with the response handling
1059 DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in "
1060 "state %i\n", bus_pkt->cmdString(), bus_pkt->getAddr(),
1061 bus_pkt->isSecure() ? "s" : "ns",
1062 old_state);
1063
1064 // If packet was a forward, the response (if any) is already
1065 // in place in the bus_pkt == pkt structure, so we don't need
1066 // to do anything. Otherwise, use the separate bus_pkt to
1067 // generate response to pkt and then delete it.
1068 if (!is_forward) {
1069 if (pkt->needsResponse()) {
1070 assert(bus_pkt->isResponse());
1071 if (bus_pkt->isError()) {
1072 pkt->makeAtomicResponse();
1073 pkt->copyError(bus_pkt);
1074 } else if (pkt->cmd == MemCmd::WriteLineReq) {
1075 // note the use of pkt, not bus_pkt here.
1076
1077 // write-line request to the cache that promoted
1078 // the write to a whole line
1079 blk = handleFill(pkt, blk, writebacks,
1080 allocOnFill(pkt->cmd));
1081 assert(blk != NULL);
1082 is_invalidate = false;
1083 satisfyCpuSideRequest(pkt, blk);
1084 } else if (bus_pkt->isRead() ||
1085 bus_pkt->cmd == MemCmd::UpgradeResp) {
1086 // we're updating cache state to allow us to
1087 // satisfy the upstream request from the cache
1088 blk = handleFill(bus_pkt, blk, writebacks,
1089 allocOnFill(pkt->cmd));
1090 satisfyCpuSideRequest(pkt, blk);
1091 } else {
1092 // we're satisfying the upstream request without
1093 // modifying cache state, e.g., a write-through
1094 pkt->makeAtomicResponse();
1095 }
1096 }
1097 delete bus_pkt;
1098 }
1099
1100 if (is_invalidate && blk && blk->isValid()) {
1101 invalidateBlock(blk);
1102 }
1103 }
1104
1105 // Note that we don't invoke the prefetcher at all in atomic mode.
1106 // It's not clear how to do it properly, particularly for
1107 // prefetchers that aggressively generate prefetch candidates and
1108 // rely on bandwidth contention to throttle them; these will tend
1109 // to pollute the cache in atomic mode since there is no bandwidth
1110 // contention. If we ever do want to enable prefetching in atomic
1111 // mode, though, this is the place to do it... see timingAccess()
1112 // for an example (though we'd want to issue the prefetch(es)
1113 // immediately rather than calling requestMemSideBus() as we do
1114 // there).
1115
1116 // do any writebacks resulting from the response handling
1117 doWritebacksAtomic(writebacks);
1118
1119 // if we used temp block, check to see if its valid and if so
1120 // clear it out, but only do so after the call to recvAtomic is
1121 // finished so that any downstream observers (such as a snoop
1122 // filter), first see the fill, and only then see the eviction
1123 if (blk == tempBlock && tempBlock->isValid()) {
1124 // the atomic CPU calls recvAtomic for fetch and load/store
1125 // sequentuially, and we may already have a tempBlock
1126 // writeback from the fetch that we have not yet sent
1127 if (tempBlockWriteback) {
1128 // if that is the case, write the prevoius one back, and
1129 // do not schedule any new event
1130 writebackTempBlockAtomic();
1131 } else {
1132 // the writeback/clean eviction happens after the call to
1133 // recvAtomic has finished (but before any successive
1134 // calls), so that the response handling from the fill is
1135 // allowed to happen first
1136 schedule(writebackTempBlockAtomicEvent, curTick());
1137 }
1138
1139 tempBlockWriteback = (blk->isDirty() || writebackClean) ?
1140 writebackBlk(blk) : cleanEvictBlk(blk);
1141 blk->invalidate();
1142 }
1143
1144 if (pkt->needsResponse()) {
1145 pkt->makeAtomicResponse();
1146 }
1147
1148 return lat * clockPeriod();
1149}
1150
1151
1152void
1153Cache::functionalAccess(PacketPtr pkt, bool fromCpuSide)
1154{
1155 if (system->bypassCaches()) {
1156 // Packets from the memory side are snoop request and
1157 // shouldn't happen in bypass mode.
1158 assert(fromCpuSide);
1159
1160 // The cache should be flushed if we are in cache bypass mode,
1161 // so we don't need to check if we need to update anything.
1162 memSidePort->sendFunctional(pkt);
1163 return;
1164 }
1165
1166 Addr blk_addr = blockAlign(pkt->getAddr());
1167 bool is_secure = pkt->isSecure();
1168 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
1169 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
1170
1171 pkt->pushLabel(name());
1172
1173 CacheBlkPrintWrapper cbpw(blk);
1174
1175 // Note that just because an L2/L3 has valid data doesn't mean an
1176 // L1 doesn't have a more up-to-date modified copy that still
1177 // needs to be found. As a result we always update the request if
1178 // we have it, but only declare it satisfied if we are the owner.
1179
1180 // see if we have data at all (owned or otherwise)
1181 bool have_data = blk && blk->isValid()
1182 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
1183 blk->data);
1184
1185 // data we have is dirty if marked as such or if we have an
1186 // in-service MSHR that is pending a modified line
1187 bool have_dirty =
1188 have_data && (blk->isDirty() ||
1189 (mshr && mshr->inService && mshr->isPendingModified()));
1190
1191 bool done = have_dirty
1192 || cpuSidePort->checkFunctional(pkt)
1193 || mshrQueue.checkFunctional(pkt, blk_addr)
1194 || writeBuffer.checkFunctional(pkt, blk_addr)
1195 || memSidePort->checkFunctional(pkt);
1196
1197 DPRINTF(CacheVerbose, "functional %s %#llx (%s) %s%s%s\n",
1198 pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns",
1199 (blk && blk->isValid()) ? "valid " : "",
1200 have_data ? "data " : "", done ? "done " : "");
1201
1202 // We're leaving the cache, so pop cache->name() label
1203 pkt->popLabel();
1204
1205 if (done) {
1206 pkt->makeResponse();
1207 } else {
1208 // if it came as a request from the CPU side then make sure it
1209 // continues towards the memory side
1210 if (fromCpuSide) {
1211 memSidePort->sendFunctional(pkt);
1212 } else if (forwardSnoops && cpuSidePort->isSnooping()) {
1213 // if it came from the memory side, it must be a snoop request
1214 // and we should only forward it if we are forwarding snoops
1215 cpuSidePort->sendFunctionalSnoop(pkt);
1216 }
1217 }
1218}
1219
1220
1221/////////////////////////////////////////////////////
1222//
1223// Response handling: responses from the memory side
1224//
1225/////////////////////////////////////////////////////
1226
1227
1228void
1229Cache::handleUncacheableWriteResp(PacketPtr pkt)
1230{
1231 Tick completion_time = clockEdge(responseLatency) +
1232 pkt->headerDelay + pkt->payloadDelay;
1233
1234 // Reset the bus additional time as it is now accounted for
1235 pkt->headerDelay = pkt->payloadDelay = 0;
1236
1237 cpuSidePort->schedTimingResp(pkt, completion_time, true);
1238}
1239
1240void
1241Cache::recvTimingResp(PacketPtr pkt)
1242{
1243 assert(pkt->isResponse());
1244
1245 // all header delay should be paid for by the crossbar, unless
1246 // this is a prefetch response from above
1247 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
1248 "%s saw a non-zero packet delay\n", name());
1249
1250 bool is_error = pkt->isError();
1251
1252 if (is_error) {
1253 DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), "
1254 "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns",
1255 pkt->cmdString());
1256 }
1257
1258 DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n",
1259 pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1260 pkt->isSecure() ? "s" : "ns");
1261
1262 // if this is a write, we should be looking at an uncacheable
1263 // write
1264 if (pkt->isWrite()) {
1265 assert(pkt->req->isUncacheable());
1266 handleUncacheableWriteResp(pkt);
1267 return;
1268 }
1269
1270 // we have dealt with any (uncacheable) writes above, from here on
1271 // we know we are dealing with an MSHR due to a miss or a prefetch
1272 MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
1273 assert(mshr);
1274
1275 if (mshr == noTargetMSHR) {
1276 // we always clear at least one target
1277 clearBlocked(Blocked_NoTargets);
|
1278 noTargetMSHR = NULL;
| 1278 noTargetMSHR = nullptr;
|
1279 }
1280
1281 // Initial target is used just for stats
1282 MSHR::Target *initial_tgt = mshr->getTarget();
1283 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
1284 Tick miss_latency = curTick() - initial_tgt->recvTime;
1285
1286 if (pkt->req->isUncacheable()) {
1287 assert(pkt->req->masterId() < system->maxMasters());
1288 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
1289 miss_latency;
1290 } else {
1291 assert(pkt->req->masterId() < system->maxMasters());
1292 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
1293 miss_latency;
1294 }
1295
1296 bool wasFull = mshrQueue.isFull();
1297
1298 PacketList writebacks;
1299
1300 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1301
1302 // upgrade deferred targets if the response has no sharers, and is
1303 // thus passing writable
1304 if (!pkt->hasSharers()) {
1305 mshr->promoteWritable();
1306 }
1307
1308 bool is_fill = !mshr->isForward &&
1309 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
1310
1311 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1312
1313 if (is_fill && !is_error) {
1314 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
1315 pkt->getAddr());
1316
1317 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill);
| 1279 }
1280
1281 // Initial target is used just for stats
1282 MSHR::Target *initial_tgt = mshr->getTarget();
1283 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
1284 Tick miss_latency = curTick() - initial_tgt->recvTime;
1285
1286 if (pkt->req->isUncacheable()) {
1287 assert(pkt->req->masterId() < system->maxMasters());
1288 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
1289 miss_latency;
1290 } else {
1291 assert(pkt->req->masterId() < system->maxMasters());
1292 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
1293 miss_latency;
1294 }
1295
1296 bool wasFull = mshrQueue.isFull();
1297
1298 PacketList writebacks;
1299
1300 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1301
1302 // upgrade deferred targets if the response has no sharers, and is
1303 // thus passing writable
1304 if (!pkt->hasSharers()) {
1305 mshr->promoteWritable();
1306 }
1307
1308 bool is_fill = !mshr->isForward &&
1309 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
1310
1311 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1312
1313 if (is_fill && !is_error) {
1314 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
1315 pkt->getAddr());
1316
1317 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill);
|
1318 assert(blk != NULL);
| 1318 assert(blk != nullptr);
|
1319 }
1320
1321 // allow invalidation responses originating from write-line
1322 // requests to be discarded
1323 bool is_invalidate = pkt->isInvalidate();
1324
1325 // First offset for critical word first calculations
1326 int initial_offset = initial_tgt->pkt->getOffset(blkSize);
1327
1328 while (mshr->hasTargets()) {
1329 MSHR::Target *target = mshr->getTarget();
1330 Packet *tgt_pkt = target->pkt;
1331
1332 switch (target->source) {
1333 case MSHR::Target::FromCPU:
1334 Tick completion_time;
1335 // Here we charge on completion_time the delay of the xbar if the
1336 // packet comes from it, charged on headerDelay.
1337 completion_time = pkt->headerDelay;
1338
1339 // Software prefetch handling for cache closest to core
1340 if (tgt_pkt->cmd.isSWPrefetch()) {
1341 // a software prefetch would have already been ack'd
1342 // immediately with dummy data so the core would be able to
1343 // retire it. This request completes right here, so we
1344 // deallocate it.
1345 delete tgt_pkt->req;
1346 delete tgt_pkt;
1347 break; // skip response
1348 }
1349
1350 // unlike the other packet flows, where data is found in other
1351 // caches or memory and brought back, write-line requests always
1352 // have the data right away, so the above check for "is fill?"
1353 // cannot actually be determined until examining the stored MSHR
1354 // state. We "catch up" with that logic here, which is duplicated
1355 // from above.
1356 if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
1357 assert(!is_error);
1358 // we got the block in a writable state, so promote
1359 // any deferred targets if possible
1360 mshr->promoteWritable();
1361 // NB: we use the original packet here and not the response!
1362 blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill);
| 1319 }
1320
1321 // allow invalidation responses originating from write-line
1322 // requests to be discarded
1323 bool is_invalidate = pkt->isInvalidate();
1324
1325 // First offset for critical word first calculations
1326 int initial_offset = initial_tgt->pkt->getOffset(blkSize);
1327
1328 while (mshr->hasTargets()) {
1329 MSHR::Target *target = mshr->getTarget();
1330 Packet *tgt_pkt = target->pkt;
1331
1332 switch (target->source) {
1333 case MSHR::Target::FromCPU:
1334 Tick completion_time;
1335 // Here we charge on completion_time the delay of the xbar if the
1336 // packet comes from it, charged on headerDelay.
1337 completion_time = pkt->headerDelay;
1338
1339 // Software prefetch handling for cache closest to core
1340 if (tgt_pkt->cmd.isSWPrefetch()) {
1341 // a software prefetch would have already been ack'd
1342 // immediately with dummy data so the core would be able to
1343 // retire it. This request completes right here, so we
1344 // deallocate it.
1345 delete tgt_pkt->req;
1346 delete tgt_pkt;
1347 break; // skip response
1348 }
1349
1350 // unlike the other packet flows, where data is found in other
1351 // caches or memory and brought back, write-line requests always
1352 // have the data right away, so the above check for "is fill?"
1353 // cannot actually be determined until examining the stored MSHR
1354 // state. We "catch up" with that logic here, which is duplicated
1355 // from above.
1356 if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
1357 assert(!is_error);
1358 // we got the block in a writable state, so promote
1359 // any deferred targets if possible
1360 mshr->promoteWritable();
1361 // NB: we use the original packet here and not the response!
1362 blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill);
|
1363 assert(blk != NULL);
| 1363 assert(blk != nullptr);
|
1364
1365 // treat as a fill, and discard the invalidation
1366 // response
1367 is_fill = true;
1368 is_invalidate = false;
1369 }
1370
1371 if (is_fill) {
1372 satisfyCpuSideRequest(tgt_pkt, blk,
1373 true, mshr->hasPostDowngrade());
1374
1375 // How many bytes past the first request is this one
1376 int transfer_offset =
1377 tgt_pkt->getOffset(blkSize) - initial_offset;
1378 if (transfer_offset < 0) {
1379 transfer_offset += blkSize;
1380 }
1381
1382 // If not critical word (offset) return payloadDelay.
1383 // responseLatency is the latency of the return path
1384 // from lower level caches/memory to an upper level cache or
1385 // the core.
1386 completion_time += clockEdge(responseLatency) +
1387 (transfer_offset ? pkt->payloadDelay : 0);
1388
1389 assert(!tgt_pkt->req->isUncacheable());
1390
1391 assert(tgt_pkt->req->masterId() < system->maxMasters());
1392 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
1393 completion_time - target->recvTime;
1394 } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
1395 // failed StoreCond upgrade
1396 assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
1397 tgt_pkt->cmd == MemCmd::StoreCondFailReq ||
1398 tgt_pkt->cmd == MemCmd::SCUpgradeFailReq);
1399 // responseLatency is the latency of the return path
1400 // from lower level caches/memory to an upper level cache or
1401 // the core.
1402 completion_time += clockEdge(responseLatency) +
1403 pkt->payloadDelay;
1404 tgt_pkt->req->setExtraData(0);
1405 } else {
1406 // not a cache fill, just forwarding response
1407 // responseLatency is the latency of the return path
1408 // from lower level cahces/memory to the core.
1409 completion_time += clockEdge(responseLatency) +
1410 pkt->payloadDelay;
1411 if (pkt->isRead() && !is_error) {
1412 // sanity check
1413 assert(pkt->getAddr() == tgt_pkt->getAddr());
1414 assert(pkt->getSize() >= tgt_pkt->getSize());
1415
1416 tgt_pkt->setData(pkt->getConstPtr<uint8_t>());
1417 }
1418 }
1419 tgt_pkt->makeTimingResponse();
1420 // if this packet is an error copy that to the new packet
1421 if (is_error)
1422 tgt_pkt->copyError(pkt);
1423 if (tgt_pkt->cmd == MemCmd::ReadResp &&
1424 (is_invalidate || mshr->hasPostInvalidate())) {
1425 // If intermediate cache got ReadRespWithInvalidate,
1426 // propagate that. Response should not have
1427 // isInvalidate() set otherwise.
1428 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate;
1429 DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n",
1430 __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr());
1431 }
1432 // Reset the bus additional time as it is now accounted for
1433 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
1434 cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
1435 break;
1436
1437 case MSHR::Target::FromPrefetcher:
1438 assert(tgt_pkt->cmd == MemCmd::HardPFReq);
1439 if (blk)
1440 blk->status |= BlkHWPrefetched;
1441 delete tgt_pkt->req;
1442 delete tgt_pkt;
1443 break;
1444
1445 case MSHR::Target::FromSnoop:
1446 // I don't believe that a snoop can be in an error state
1447 assert(!is_error);
1448 // response to snoop request
1449 DPRINTF(Cache, "processing deferred snoop...\n");
1450 assert(!(is_invalidate && !mshr->hasPostInvalidate()));
1451 handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
1452 break;
1453
1454 default:
1455 panic("Illegal target->source enum %d\n", target->source);
1456 }
1457
1458 mshr->popTarget();
1459 }
1460
1461 if (blk && blk->isValid()) {
1462 // an invalidate response stemming from a write line request
1463 // should not invalidate the block, so check if the
1464 // invalidation should be discarded
1465 if (is_invalidate || mshr->hasPostInvalidate()) {
1466 invalidateBlock(blk);
1467 } else if (mshr->hasPostDowngrade()) {
1468 blk->status &= ~BlkWritable;
1469 }
1470 }
1471
1472 if (mshr->promoteDeferredTargets()) {
1473 // avoid later read getting stale data while write miss is
1474 // outstanding.. see comment in timingAccess()
1475 if (blk) {
1476 blk->status &= ~BlkReadable;
1477 }
1478 mshrQueue.markPending(mshr);
1479 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
1480 } else {
1481 mshrQueue.deallocate(mshr);
1482 if (wasFull && !mshrQueue.isFull()) {
1483 clearBlocked(Blocked_NoMSHRs);
1484 }
1485
1486 // Request the bus for a prefetch if this deallocation freed enough
1487 // MSHRs for a prefetch to take place
1488 if (prefetcher && mshrQueue.canPrefetch()) {
1489 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
1490 clockEdge());
1491 if (next_pf_time != MaxTick)
1492 schedMemSideSendEvent(next_pf_time);
1493 }
1494 }
1495 // reset the xbar additional timinig as it is now accounted for
1496 pkt->headerDelay = pkt->payloadDelay = 0;
1497
1498 // copy writebacks to write buffer
1499 doWritebacks(writebacks, forward_time);
1500
1501 // if we used temp block, check to see if its valid and then clear it out
1502 if (blk == tempBlock && tempBlock->isValid()) {
1503 // We use forwardLatency here because we are copying
1504 // Writebacks/CleanEvicts to write buffer. It specifies the latency to
1505 // allocate an internal buffer and to schedule an event to the
1506 // queued port.
1507 if (blk->isDirty() || writebackClean) {
1508 PacketPtr wbPkt = writebackBlk(blk);
1509 allocateWriteBuffer(wbPkt, forward_time);
1510 // Set BLOCK_CACHED flag if cached above.
1511 if (isCachedAbove(wbPkt))
1512 wbPkt->setBlockCached();
1513 } else {
1514 PacketPtr wcPkt = cleanEvictBlk(blk);
1515 // Check to see if block is cached above. If not allocate
1516 // write buffer
1517 if (isCachedAbove(wcPkt))
1518 delete wcPkt;
1519 else
1520 allocateWriteBuffer(wcPkt, forward_time);
1521 }
1522 blk->invalidate();
1523 }
1524
1525 DPRINTF(CacheVerbose, "Leaving %s with %s for addr %#llx\n", __func__,
1526 pkt->cmdString(), pkt->getAddr());
1527 delete pkt;
1528}
1529
1530PacketPtr
1531Cache::writebackBlk(CacheBlk *blk)
1532{
1533 chatty_assert(!isReadOnly || writebackClean,
1534 "Writeback from read-only cache");
1535 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
1536
1537 writebacks[Request::wbMasterId]++;
1538
1539 Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set),
1540 blkSize, 0, Request::wbMasterId);
1541 if (blk->isSecure())
1542 req->setFlags(Request::SECURE);
1543
1544 req->taskId(blk->task_id);
1545 blk->task_id= ContextSwitchTaskId::Unknown;
1546 blk->tickInserted = curTick();
1547
1548 PacketPtr pkt =
1549 new Packet(req, blk->isDirty() ?
1550 MemCmd::WritebackDirty : MemCmd::WritebackClean);
1551
1552 DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n",
1553 pkt->getAddr(), blk->isWritable(), blk->isDirty());
1554
1555 if (blk->isWritable()) {
1556 // not asserting shared means we pass the block in modified
1557 // state, mark our own block non-writeable
1558 blk->status &= ~BlkWritable;
1559 } else {
1560 // we are in the Owned state, tell the receiver
1561 pkt->setHasSharers();
1562 }
1563
1564 // make sure the block is not marked dirty
1565 blk->status &= ~BlkDirty;
1566
1567 pkt->allocate();
1568 std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
1569
1570 return pkt;
1571}
1572
1573PacketPtr
1574Cache::cleanEvictBlk(CacheBlk *blk)
1575{
1576 assert(!writebackClean);
1577 assert(blk && blk->isValid() && !blk->isDirty());
1578 // Creating a zero sized write, a message to the snoop filter
1579 Request *req =
1580 new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
1581 Request::wbMasterId);
1582 if (blk->isSecure())
1583 req->setFlags(Request::SECURE);
1584
1585 req->taskId(blk->task_id);
1586 blk->task_id = ContextSwitchTaskId::Unknown;
1587 blk->tickInserted = curTick();
1588
1589 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict);
1590 pkt->allocate();
1591 DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(),
1592 pkt->req->isInstFetch() ? " (ifetch)" : "",
1593 pkt->getAddr());
1594
1595 return pkt;
1596}
1597
1598void
1599Cache::memWriteback()
1600{
1601 CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor);
1602 tags->forEachBlk(visitor);
1603}
1604
1605void
1606Cache::memInvalidate()
1607{
1608 CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor);
1609 tags->forEachBlk(visitor);
1610}
1611
1612bool
1613Cache::isDirty() const
1614{
1615 CacheBlkIsDirtyVisitor visitor;
1616 tags->forEachBlk(visitor);
1617
1618 return visitor.isDirty();
1619}
1620
1621bool
1622Cache::writebackVisitor(CacheBlk &blk)
1623{
1624 if (blk.isDirty()) {
1625 assert(blk.isValid());
1626
1627 Request request(tags->regenerateBlkAddr(blk.tag, blk.set),
1628 blkSize, 0, Request::funcMasterId);
1629 request.taskId(blk.task_id);
1630
1631 Packet packet(&request, MemCmd::WriteReq);
1632 packet.dataStatic(blk.data);
1633
1634 memSidePort->sendFunctional(&packet);
1635
1636 blk.status &= ~BlkDirty;
1637 }
1638
1639 return true;
1640}
1641
1642bool
1643Cache::invalidateVisitor(CacheBlk &blk)
1644{
1645
1646 if (blk.isDirty())
1647 warn_once("Invalidating dirty cache lines. Expect things to break.\n");
1648
1649 if (blk.isValid()) {
1650 assert(!blk.isDirty());
1651 tags->invalidate(&blk);
1652 blk.invalidate();
1653 }
1654
1655 return true;
1656}
1657
1658CacheBlk*
1659Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1660{
1661 CacheBlk *blk = tags->findVictim(addr);
1662
| 1364
1365 // treat as a fill, and discard the invalidation
1366 // response
1367 is_fill = true;
1368 is_invalidate = false;
1369 }
1370
1371 if (is_fill) {
1372 satisfyCpuSideRequest(tgt_pkt, blk,
1373 true, mshr->hasPostDowngrade());
1374
1375 // How many bytes past the first request is this one
1376 int transfer_offset =
1377 tgt_pkt->getOffset(blkSize) - initial_offset;
1378 if (transfer_offset < 0) {
1379 transfer_offset += blkSize;
1380 }
1381
1382 // If not critical word (offset) return payloadDelay.
1383 // responseLatency is the latency of the return path
1384 // from lower level caches/memory to an upper level cache or
1385 // the core.
1386 completion_time += clockEdge(responseLatency) +
1387 (transfer_offset ? pkt->payloadDelay : 0);
1388
1389 assert(!tgt_pkt->req->isUncacheable());
1390
1391 assert(tgt_pkt->req->masterId() < system->maxMasters());
1392 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
1393 completion_time - target->recvTime;
1394 } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
1395 // failed StoreCond upgrade
1396 assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
1397 tgt_pkt->cmd == MemCmd::StoreCondFailReq ||
1398 tgt_pkt->cmd == MemCmd::SCUpgradeFailReq);
1399 // responseLatency is the latency of the return path
1400 // from lower level caches/memory to an upper level cache or
1401 // the core.
1402 completion_time += clockEdge(responseLatency) +
1403 pkt->payloadDelay;
1404 tgt_pkt->req->setExtraData(0);
1405 } else {
1406 // not a cache fill, just forwarding response
1407 // responseLatency is the latency of the return path
1408 // from lower level cahces/memory to the core.
1409 completion_time += clockEdge(responseLatency) +
1410 pkt->payloadDelay;
1411 if (pkt->isRead() && !is_error) {
1412 // sanity check
1413 assert(pkt->getAddr() == tgt_pkt->getAddr());
1414 assert(pkt->getSize() >= tgt_pkt->getSize());
1415
1416 tgt_pkt->setData(pkt->getConstPtr<uint8_t>());
1417 }
1418 }
1419 tgt_pkt->makeTimingResponse();
1420 // if this packet is an error copy that to the new packet
1421 if (is_error)
1422 tgt_pkt->copyError(pkt);
1423 if (tgt_pkt->cmd == MemCmd::ReadResp &&
1424 (is_invalidate || mshr->hasPostInvalidate())) {
1425 // If intermediate cache got ReadRespWithInvalidate,
1426 // propagate that. Response should not have
1427 // isInvalidate() set otherwise.
1428 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate;
1429 DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n",
1430 __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr());
1431 }
1432 // Reset the bus additional time as it is now accounted for
1433 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
1434 cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
1435 break;
1436
1437 case MSHR::Target::FromPrefetcher:
1438 assert(tgt_pkt->cmd == MemCmd::HardPFReq);
1439 if (blk)
1440 blk->status |= BlkHWPrefetched;
1441 delete tgt_pkt->req;
1442 delete tgt_pkt;
1443 break;
1444
1445 case MSHR::Target::FromSnoop:
1446 // I don't believe that a snoop can be in an error state
1447 assert(!is_error);
1448 // response to snoop request
1449 DPRINTF(Cache, "processing deferred snoop...\n");
1450 assert(!(is_invalidate && !mshr->hasPostInvalidate()));
1451 handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
1452 break;
1453
1454 default:
1455 panic("Illegal target->source enum %d\n", target->source);
1456 }
1457
1458 mshr->popTarget();
1459 }
1460
1461 if (blk && blk->isValid()) {
1462 // an invalidate response stemming from a write line request
1463 // should not invalidate the block, so check if the
1464 // invalidation should be discarded
1465 if (is_invalidate || mshr->hasPostInvalidate()) {
1466 invalidateBlock(blk);
1467 } else if (mshr->hasPostDowngrade()) {
1468 blk->status &= ~BlkWritable;
1469 }
1470 }
1471
1472 if (mshr->promoteDeferredTargets()) {
1473 // avoid later read getting stale data while write miss is
1474 // outstanding.. see comment in timingAccess()
1475 if (blk) {
1476 blk->status &= ~BlkReadable;
1477 }
1478 mshrQueue.markPending(mshr);
1479 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
1480 } else {
1481 mshrQueue.deallocate(mshr);
1482 if (wasFull && !mshrQueue.isFull()) {
1483 clearBlocked(Blocked_NoMSHRs);
1484 }
1485
1486 // Request the bus for a prefetch if this deallocation freed enough
1487 // MSHRs for a prefetch to take place
1488 if (prefetcher && mshrQueue.canPrefetch()) {
1489 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
1490 clockEdge());
1491 if (next_pf_time != MaxTick)
1492 schedMemSideSendEvent(next_pf_time);
1493 }
1494 }
1495 // reset the xbar additional timinig as it is now accounted for
1496 pkt->headerDelay = pkt->payloadDelay = 0;
1497
1498 // copy writebacks to write buffer
1499 doWritebacks(writebacks, forward_time);
1500
1501 // if we used temp block, check to see if its valid and then clear it out
1502 if (blk == tempBlock && tempBlock->isValid()) {
1503 // We use forwardLatency here because we are copying
1504 // Writebacks/CleanEvicts to write buffer. It specifies the latency to
1505 // allocate an internal buffer and to schedule an event to the
1506 // queued port.
1507 if (blk->isDirty() || writebackClean) {
1508 PacketPtr wbPkt = writebackBlk(blk);
1509 allocateWriteBuffer(wbPkt, forward_time);
1510 // Set BLOCK_CACHED flag if cached above.
1511 if (isCachedAbove(wbPkt))
1512 wbPkt->setBlockCached();
1513 } else {
1514 PacketPtr wcPkt = cleanEvictBlk(blk);
1515 // Check to see if block is cached above. If not allocate
1516 // write buffer
1517 if (isCachedAbove(wcPkt))
1518 delete wcPkt;
1519 else
1520 allocateWriteBuffer(wcPkt, forward_time);
1521 }
1522 blk->invalidate();
1523 }
1524
1525 DPRINTF(CacheVerbose, "Leaving %s with %s for addr %#llx\n", __func__,
1526 pkt->cmdString(), pkt->getAddr());
1527 delete pkt;
1528}
1529
1530PacketPtr
1531Cache::writebackBlk(CacheBlk *blk)
1532{
1533 chatty_assert(!isReadOnly || writebackClean,
1534 "Writeback from read-only cache");
1535 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
1536
1537 writebacks[Request::wbMasterId]++;
1538
1539 Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set),
1540 blkSize, 0, Request::wbMasterId);
1541 if (blk->isSecure())
1542 req->setFlags(Request::SECURE);
1543
1544 req->taskId(blk->task_id);
1545 blk->task_id= ContextSwitchTaskId::Unknown;
1546 blk->tickInserted = curTick();
1547
1548 PacketPtr pkt =
1549 new Packet(req, blk->isDirty() ?
1550 MemCmd::WritebackDirty : MemCmd::WritebackClean);
1551
1552 DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n",
1553 pkt->getAddr(), blk->isWritable(), blk->isDirty());
1554
1555 if (blk->isWritable()) {
1556 // not asserting shared means we pass the block in modified
1557 // state, mark our own block non-writeable
1558 blk->status &= ~BlkWritable;
1559 } else {
1560 // we are in the Owned state, tell the receiver
1561 pkt->setHasSharers();
1562 }
1563
1564 // make sure the block is not marked dirty
1565 blk->status &= ~BlkDirty;
1566
1567 pkt->allocate();
1568 std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
1569
1570 return pkt;
1571}
1572
1573PacketPtr
1574Cache::cleanEvictBlk(CacheBlk *blk)
1575{
1576 assert(!writebackClean);
1577 assert(blk && blk->isValid() && !blk->isDirty());
1578 // Creating a zero sized write, a message to the snoop filter
1579 Request *req =
1580 new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
1581 Request::wbMasterId);
1582 if (blk->isSecure())
1583 req->setFlags(Request::SECURE);
1584
1585 req->taskId(blk->task_id);
1586 blk->task_id = ContextSwitchTaskId::Unknown;
1587 blk->tickInserted = curTick();
1588
1589 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict);
1590 pkt->allocate();
1591 DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(),
1592 pkt->req->isInstFetch() ? " (ifetch)" : "",
1593 pkt->getAddr());
1594
1595 return pkt;
1596}
1597
1598void
1599Cache::memWriteback()
1600{
1601 CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor);
1602 tags->forEachBlk(visitor);
1603}
1604
1605void
1606Cache::memInvalidate()
1607{
1608 CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor);
1609 tags->forEachBlk(visitor);
1610}
1611
1612bool
1613Cache::isDirty() const
1614{
1615 CacheBlkIsDirtyVisitor visitor;
1616 tags->forEachBlk(visitor);
1617
1618 return visitor.isDirty();
1619}
1620
1621bool
1622Cache::writebackVisitor(CacheBlk &blk)
1623{
1624 if (blk.isDirty()) {
1625 assert(blk.isValid());
1626
1627 Request request(tags->regenerateBlkAddr(blk.tag, blk.set),
1628 blkSize, 0, Request::funcMasterId);
1629 request.taskId(blk.task_id);
1630
1631 Packet packet(&request, MemCmd::WriteReq);
1632 packet.dataStatic(blk.data);
1633
1634 memSidePort->sendFunctional(&packet);
1635
1636 blk.status &= ~BlkDirty;
1637 }
1638
1639 return true;
1640}
1641
1642bool
1643Cache::invalidateVisitor(CacheBlk &blk)
1644{
1645
1646 if (blk.isDirty())
1647 warn_once("Invalidating dirty cache lines. Expect things to break.\n");
1648
1649 if (blk.isValid()) {
1650 assert(!blk.isDirty());
1651 tags->invalidate(&blk);
1652 blk.invalidate();
1653 }
1654
1655 return true;
1656}
1657
1658CacheBlk*
1659Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1660{
1661 CacheBlk *blk = tags->findVictim(addr);
1662
|
1663 // It is valid to return NULL if there is no victim
| 1663 // It is valid to return nullptr if there is no victim
|
1664 if (!blk)
1665 return nullptr;
1666
1667 if (blk->isValid()) {
1668 Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set);
1669 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1670 if (repl_mshr) {
1671 // must be an outstanding upgrade request
1672 // on a block we're about to replace...
1673 assert(!blk->isWritable() || blk->isDirty());
1674 assert(repl_mshr->needsWritable());
1675 // too hard to replace block with transient state
1676 // allocation failed, block not inserted
| 1664 if (!blk)
1665 return nullptr;
1666
1667 if (blk->isValid()) {
1668 Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set);
1669 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1670 if (repl_mshr) {
1671 // must be an outstanding upgrade request
1672 // on a block we're about to replace...
1673 assert(!blk->isWritable() || blk->isDirty());
1674 assert(repl_mshr->needsWritable());
1675 // too hard to replace block with transient state
1676 // allocation failed, block not inserted
|
1677 return NULL;
| 1677 return nullptr;
|
1678 } else {
1679 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
1680 "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns",
1681 addr, is_secure ? "s" : "ns",
1682 blk->isDirty() ? "writeback" : "clean");
1683
1684 if (blk->wasPrefetched()) {
1685 unusedPrefetches++;
1686 }
1687 // Will send up Writeback/CleanEvict snoops via isCachedAbove
1688 // when pushing this writeback list into the write buffer.
1689 if (blk->isDirty() || writebackClean) {
1690 // Save writeback packet for handling by caller
1691 writebacks.push_back(writebackBlk(blk));
1692 } else {
1693 writebacks.push_back(cleanEvictBlk(blk));
1694 }
1695 }
1696 }
1697
1698 return blk;
1699}
1700
1701void
1702Cache::invalidateBlock(CacheBlk *blk)
1703{
1704 if (blk != tempBlock)
1705 tags->invalidate(blk);
1706 blk->invalidate();
1707}
1708
1709// Note that the reason we return a list of writebacks rather than
1710// inserting them directly in the write buffer is that this function
1711// is called by both atomic and timing-mode accesses, and in atomic
1712// mode we don't mess with the write buffer (we just perform the
1713// writebacks atomically once the original request is complete).
1714CacheBlk*
1715Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
1716 bool allocate)
1717{
1718 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
1719 Addr addr = pkt->getAddr();
1720 bool is_secure = pkt->isSecure();
1721#if TRACING_ON
1722 CacheBlk::State old_state = blk ? blk->status : 0;
1723#endif
1724
1725 // When handling a fill, we should have no writes to this line.
1726 assert(addr == blockAlign(addr));
1727 assert(!writeBuffer.findMatch(addr, is_secure));
1728
| 1678 } else {
1679 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
1680 "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns",
1681 addr, is_secure ? "s" : "ns",
1682 blk->isDirty() ? "writeback" : "clean");
1683
1684 if (blk->wasPrefetched()) {
1685 unusedPrefetches++;
1686 }
1687 // Will send up Writeback/CleanEvict snoops via isCachedAbove
1688 // when pushing this writeback list into the write buffer.
1689 if (blk->isDirty() || writebackClean) {
1690 // Save writeback packet for handling by caller
1691 writebacks.push_back(writebackBlk(blk));
1692 } else {
1693 writebacks.push_back(cleanEvictBlk(blk));
1694 }
1695 }
1696 }
1697
1698 return blk;
1699}
1700
1701void
1702Cache::invalidateBlock(CacheBlk *blk)
1703{
1704 if (blk != tempBlock)
1705 tags->invalidate(blk);
1706 blk->invalidate();
1707}
1708
1709// Note that the reason we return a list of writebacks rather than
1710// inserting them directly in the write buffer is that this function
1711// is called by both atomic and timing-mode accesses, and in atomic
1712// mode we don't mess with the write buffer (we just perform the
1713// writebacks atomically once the original request is complete).
1714CacheBlk*
1715Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
1716 bool allocate)
1717{
1718 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
1719 Addr addr = pkt->getAddr();
1720 bool is_secure = pkt->isSecure();
1721#if TRACING_ON
1722 CacheBlk::State old_state = blk ? blk->status : 0;
1723#endif
1724
1725 // When handling a fill, we should have no writes to this line.
1726 assert(addr == blockAlign(addr));
1727 assert(!writeBuffer.findMatch(addr, is_secure));
1728
|
1729 if (blk == NULL) {
| 1729 if (blk == nullptr) {
|
1730 // better have read new data...
1731 assert(pkt->hasData());
1732
1733 // only read responses and write-line requests have data;
1734 // note that we don't write the data here for write-line - that
1735 // happens in the subsequent satisfyCpuSideRequest.
1736 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
1737
1738 // need to do a replacement if allocating, otherwise we stick
1739 // with the temporary storage
| 1730 // better have read new data...
1731 assert(pkt->hasData());
1732
1733 // only read responses and write-line requests have data;
1734 // note that we don't write the data here for write-line - that
1735 // happens in the subsequent satisfyCpuSideRequest.
1736 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
1737
1738 // need to do a replacement if allocating, otherwise we stick
1739 // with the temporary storage
|
1740 blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL;
| 1740 blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr;
|
1741
| 1741
|
1742 if (blk == NULL) {
| 1742 if (blk == nullptr) {
|
1743 // No replaceable block or a mostly exclusive
1744 // cache... just use temporary storage to complete the
1745 // current request and then get rid of it
1746 assert(!tempBlock->isValid());
1747 blk = tempBlock;
1748 tempBlock->set = tags->extractSet(addr);
1749 tempBlock->tag = tags->extractTag(addr);
1750 // @todo: set security state as well...
1751 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
1752 is_secure ? "s" : "ns");
1753 } else {
1754 tags->insertBlock(pkt, blk);
1755 }
1756
1757 // we should never be overwriting a valid block
1758 assert(!blk->isValid());
1759 } else {
1760 // existing block... probably an upgrade
1761 assert(blk->tag == tags->extractTag(addr));
1762 // either we're getting new data or the block should already be valid
1763 assert(pkt->hasData() || blk->isValid());
1764 // don't clear block status... if block is already dirty we
1765 // don't want to lose that
1766 }
1767
1768 if (is_secure)
1769 blk->status |= BlkSecure;
1770 blk->status |= BlkValid | BlkReadable;
1771
1772 // sanity check for whole-line writes, which should always be
1773 // marked as writable as part of the fill, and then later marked
1774 // dirty as part of satisfyCpuSideRequest
1775 if (pkt->cmd == MemCmd::WriteLineReq) {
1776 assert(!pkt->hasSharers());
1777 // at the moment other caches do not respond to the
1778 // invalidation requests corresponding to a whole-line write
1779 assert(!pkt->cacheResponding());
1780 }
1781
1782 // here we deal with setting the appropriate state of the line,
1783 // and we start by looking at the hasSharers flag, and ignore the
1784 // cacheResponding flag (normally signalling dirty data) if the
1785 // packet has sharers, thus the line is never allocated as Owned
1786 // (dirty but not writable), and always ends up being either
1787 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1788 // for more details
1789 if (!pkt->hasSharers()) {
1790 // we could get a writable line from memory (rather than a
1791 // cache) even in a read-only cache, note that we set this bit
1792 // even for a read-only cache, possibly revisit this decision
1793 blk->status |= BlkWritable;
1794
1795 // check if we got this via cache-to-cache transfer (i.e., from a
1796 // cache that had the block in Modified or Owned state)
1797 if (pkt->cacheResponding()) {
1798 // we got the block in Modified state, and invalidated the
1799 // owners copy
1800 blk->status |= BlkDirty;
1801
1802 chatty_assert(!isReadOnly, "Should never see dirty snoop response "
1803 "in read-only cache %s\n", name());
1804 }
1805 }
1806
1807 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
1808 addr, is_secure ? "s" : "ns", old_state, blk->print());
1809
1810 // if we got new data, copy it in (checking for a read response
1811 // and a response that has data is the same in the end)
1812 if (pkt->isRead()) {
1813 // sanity checks
1814 assert(pkt->hasData());
1815 assert(pkt->getSize() == blkSize);
1816
1817 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize);
1818 }
1819 // We pay for fillLatency here.
1820 blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1821 pkt->payloadDelay;
1822
1823 return blk;
1824}
1825
1826
1827/////////////////////////////////////////////////////
1828//
1829// Snoop path: requests coming in from the memory side
1830//
1831/////////////////////////////////////////////////////
1832
1833void
1834Cache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
1835 bool already_copied, bool pending_inval)
1836{
1837 // sanity check
1838 assert(req_pkt->isRequest());
1839 assert(req_pkt->needsResponse());
1840
1841 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
1842 req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize());
1843 // timing-mode snoop responses require a new packet, unless we
1844 // already made a copy...
1845 PacketPtr pkt = req_pkt;
1846 if (!already_copied)
1847 // do not clear flags, and allocate space for data if the
1848 // packet needs it (the only packets that carry data are read
1849 // responses)
1850 pkt = new Packet(req_pkt, false, req_pkt->isRead());
1851
1852 assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() ||
1853 pkt->hasSharers());
1854 pkt->makeTimingResponse();
1855 if (pkt->isRead()) {
1856 pkt->setDataFromBlock(blk_data, blkSize);
1857 }
1858 if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
1859 // Assume we defer a response to a read from a far-away cache
1860 // A, then later defer a ReadExcl from a cache B on the same
1861 // bus as us. We'll assert cacheResponding in both cases, but
1862 // in the latter case cacheResponding will keep the
1863 // invalidation from reaching cache A. This special response
1864 // tells cache A that it gets the block to satisfy its read,
1865 // but must immediately invalidate it.
1866 pkt->cmd = MemCmd::ReadRespWithInvalidate;
1867 }
1868 // Here we consider forward_time, paying for just forward latency and
1869 // also charging the delay provided by the xbar.
1870 // forward_time is used as send_time in next allocateWriteBuffer().
1871 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1872 // Here we reset the timing of the packet.
1873 pkt->headerDelay = pkt->payloadDelay = 0;
1874 DPRINTF(CacheVerbose,
1875 "%s created response: %s addr %#llx size %d tick: %lu\n",
1876 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1877 forward_time);
1878 memSidePort->schedTimingSnoopResp(pkt, forward_time, true);
1879}
1880
1881uint32_t
1882Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
1883 bool is_deferred, bool pending_inval)
1884{
1885 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__,
1886 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1887 // deferred snoops can only happen in timing mode
1888 assert(!(is_deferred && !is_timing));
1889 // pending_inval only makes sense on deferred snoops
1890 assert(!(pending_inval && !is_deferred));
1891 assert(pkt->isRequest());
1892
1893 // the packet may get modified if we or a forwarded snooper
1894 // responds in atomic mode, so remember a few things about the
1895 // original packet up front
1896 bool invalidate = pkt->isInvalidate();
1897 bool M5_VAR_USED needs_writable = pkt->needsWritable();
1898
1899 // at the moment we could get an uncacheable write which does not
1900 // have the invalidate flag, and we need a suitable way of dealing
1901 // with this case
1902 panic_if(invalidate && pkt->req->isUncacheable(),
1903 "%s got an invalidating uncacheable snoop request %s to %#llx",
1904 name(), pkt->cmdString(), pkt->getAddr());
1905
1906 uint32_t snoop_delay = 0;
1907
1908 if (forwardSnoops) {
1909 // first propagate snoop upward to see if anyone above us wants to
1910 // handle it. save & restore packet src since it will get
1911 // rewritten to be relative to cpu-side bus (if any)
1912 bool alreadyResponded = pkt->cacheResponding();
1913 if (is_timing) {
1914 // copy the packet so that we can clear any flags before
1915 // forwarding it upwards, we also allocate data (passing
1916 // the pointer along in case of static data), in case
1917 // there is a snoop hit in upper levels
1918 Packet snoopPkt(pkt, true, true);
1919 snoopPkt.setExpressSnoop();
1920 // the snoop packet does not need to wait any additional
1921 // time
1922 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
1923 cpuSidePort->sendTimingSnoopReq(&snoopPkt);
1924
1925 // add the header delay (including crossbar and snoop
1926 // delays) of the upward snoop to the snoop delay for this
1927 // cache
1928 snoop_delay += snoopPkt.headerDelay;
1929
1930 if (snoopPkt.cacheResponding()) {
1931 // cache-to-cache response from some upper cache
1932 assert(!alreadyResponded);
1933 pkt->setCacheResponding();
1934 }
1935 // upstream cache has the block, or has an outstanding
1936 // MSHR, pass the flag on
1937 if (snoopPkt.hasSharers()) {
1938 pkt->setHasSharers();
1939 }
1940 // If this request is a prefetch or clean evict and an upper level
1941 // signals block present, make sure to propagate the block
1942 // presence to the requester.
1943 if (snoopPkt.isBlockCached()) {
1944 pkt->setBlockCached();
1945 }
1946 } else {
1947 cpuSidePort->sendAtomicSnoop(pkt);
1948 if (!alreadyResponded && pkt->cacheResponding()) {
1949 // cache-to-cache response from some upper cache:
1950 // forward response to original requester
1951 assert(pkt->isResponse());
1952 }
1953 }
1954 }
1955
1956 if (!blk || !blk->isValid()) {
1957 DPRINTF(CacheVerbose, "%s snoop miss for %s addr %#llx size %d\n",
1958 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1959 return snoop_delay;
1960 } else {
1961 DPRINTF(Cache, "%s snoop hit for %s addr %#llx size %d, "
1962 "old state is %s\n", __func__, pkt->cmdString(),
1963 pkt->getAddr(), pkt->getSize(), blk->print());
1964 }
1965
1966 chatty_assert(!(isReadOnly && blk->isDirty()),
1967 "Should never have a dirty block in a read-only cache %s\n",
1968 name());
1969
1970 // We may end up modifying both the block state and the packet (if
1971 // we respond in atomic mode), so just figure out what to do now
1972 // and then do it later. If we find dirty data while snooping for
1973 // an invalidate, we don't need to send a response. The
1974 // invalidation itself is taken care of below.
1975 bool respond = blk->isDirty() && pkt->needsResponse() &&
1976 pkt->cmd != MemCmd::InvalidateReq;
1977 bool have_writable = blk->isWritable();
1978
1979 // Invalidate any prefetch's from below that would strip write permissions
1980 // MemCmd::HardPFReq is only observed by upstream caches. After missing
1981 // above and in it's own cache, a new MemCmd::ReadReq is created that
1982 // downstream caches observe.
1983 if (pkt->mustCheckAbove()) {
1984 DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s "
1985 "from lower cache\n", pkt->getAddr(), pkt->cmdString());
1986 pkt->setBlockCached();
1987 return snoop_delay;
1988 }
1989
1990 if (pkt->isRead() && !invalidate) {
1991 // reading without requiring the line in a writable state
1992 assert(!needs_writable);
1993 pkt->setHasSharers();
1994
1995 // if the requesting packet is uncacheable, retain the line in
1996 // the current state, otherwhise unset the writable flag,
1997 // which means we go from Modified to Owned (and will respond
1998 // below), remain in Owned (and will respond below), from
1999 // Exclusive to Shared, or remain in Shared
2000 if (!pkt->req->isUncacheable())
2001 blk->status &= ~BlkWritable;
2002 }
2003
2004 if (respond) {
2005 // prevent anyone else from responding, cache as well as
2006 // memory, and also prevent any memory from even seeing the
2007 // request
2008 pkt->setCacheResponding();
2009 if (have_writable) {
2010 // inform the cache hierarchy that this cache had the line
2011 // in the Modified state so that we avoid unnecessary
2012 // invalidations (see Packet::setResponderHadWritable)
2013 pkt->setResponderHadWritable();
2014
2015 // in the case of an uncacheable request there is no point
2016 // in setting the responderHadWritable flag, but since the
2017 // recipient does not care there is no harm in doing so
2018 } else {
2019 // if the packet has needsWritable set we invalidate our
2020 // copy below and all other copies will be invalidates
2021 // through express snoops, and if needsWritable is not set
2022 // we already called setHasSharers above
2023 }
2024
2025 // if we are returning a writable and dirty (Modified) line,
2026 // we should be invalidating the line
2027 panic_if(!invalidate && !pkt->hasSharers(),
2028 "%s is passing a Modified line through %s to %#llx, "
2029 "but keeping the block",
2030 name(), pkt->cmdString(), pkt->getAddr());
2031
2032 if (is_timing) {
2033 doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
2034 } else {
2035 pkt->makeAtomicResponse();
2036 // packets such as upgrades do not actually have any data
2037 // payload
2038 if (pkt->hasData())
2039 pkt->setDataFromBlock(blk->data, blkSize);
2040 }
2041 }
2042
2043 if (!respond && is_timing && is_deferred) {
2044 // if it's a deferred timing snoop to which we are not
2045 // responding, then we've made a copy of both the request and
2046 // the packet, delete them here
2047 assert(pkt->needsResponse());
2048 delete pkt->req;
2049 delete pkt;
2050 }
2051
2052 // Do this last in case it deallocates block data or something
2053 // like that
2054 if (invalidate) {
2055 invalidateBlock(blk);
2056 }
2057
2058 DPRINTF(Cache, "new state is %s\n", blk->print());
2059
2060 return snoop_delay;
2061}
2062
2063
2064void
2065Cache::recvTimingSnoopReq(PacketPtr pkt)
2066{
2067 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__,
2068 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
2069
2070 // Snoops shouldn't happen when bypassing caches
2071 assert(!system->bypassCaches());
2072
2073 // no need to snoop requests that are not in range
2074 if (!inRange(pkt->getAddr())) {
2075 return;
2076 }
2077
2078 bool is_secure = pkt->isSecure();
2079 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
2080
2081 Addr blk_addr = blockAlign(pkt->getAddr());
2082 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
2083
2084 // Update the latency cost of the snoop so that the crossbar can
2085 // account for it. Do not overwrite what other neighbouring caches
2086 // have already done, rather take the maximum. The update is
2087 // tentative, for cases where we return before an upward snoop
2088 // happens below.
2089 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay,
2090 lookupLatency * clockPeriod());
2091
2092 // Inform request(Prefetch, CleanEvict or Writeback) from below of
2093 // MSHR hit, set setBlockCached.
2094 if (mshr && pkt->mustCheckAbove()) {
2095 DPRINTF(Cache, "Setting block cached for %s from"
2096 "lower cache on mshr hit %#x\n",
2097 pkt->cmdString(), pkt->getAddr());
2098 pkt->setBlockCached();
2099 return;
2100 }
2101
2102 // Let the MSHR itself track the snoop and decide whether we want
2103 // to go ahead and do the regular cache snoop
2104 if (mshr && mshr->handleSnoop(pkt, order++)) {
2105 DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)."
2106 "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns",
2107 mshr->print());
2108
2109 if (mshr->getNumTargets() > numTarget)
2110 warn("allocating bonus target for snoop"); //handle later
2111 return;
2112 }
2113
2114 //We also need to check the writeback buffers and handle those
2115 WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure);
2116 if (wb_entry) {
2117 DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n",
2118 pkt->getAddr(), is_secure ? "s" : "ns");
2119 // Expect to see only Writebacks and/or CleanEvicts here, both of
2120 // which should not be generated for uncacheable data.
2121 assert(!wb_entry->isUncacheable());
2122 // There should only be a single request responsible for generating
2123 // Writebacks/CleanEvicts.
2124 assert(wb_entry->getNumTargets() == 1);
2125 PacketPtr wb_pkt = wb_entry->getTarget()->pkt;
2126 assert(wb_pkt->isEviction());
2127
2128 if (pkt->isEviction()) {
2129 // if the block is found in the write queue, set the BLOCK_CACHED
2130 // flag for Writeback/CleanEvict snoop. On return the snoop will
2131 // propagate the BLOCK_CACHED flag in Writeback packets and prevent
2132 // any CleanEvicts from travelling down the memory hierarchy.
2133 pkt->setBlockCached();
2134 DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit"
2135 " %#x\n", pkt->cmdString(), pkt->getAddr());
2136 return;
2137 }
2138
2139 // conceptually writebacks are no different to other blocks in
2140 // this cache, so the behaviour is modelled after handleSnoop,
2141 // the difference being that instead of querying the block
2142 // state to determine if it is dirty and writable, we use the
2143 // command and fields of the writeback packet
2144 bool respond = wb_pkt->cmd == MemCmd::WritebackDirty &&
2145 pkt->needsResponse() && pkt->cmd != MemCmd::InvalidateReq;
2146 bool have_writable = !wb_pkt->hasSharers();
2147 bool invalidate = pkt->isInvalidate();
2148
2149 if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) {
2150 assert(!pkt->needsWritable());
2151 pkt->setHasSharers();
2152 wb_pkt->setHasSharers();
2153 }
2154
2155 if (respond) {
2156 pkt->setCacheResponding();
2157
2158 if (have_writable) {
2159 pkt->setResponderHadWritable();
2160 }
2161
2162 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(),
2163 false, false);
2164 }
2165
2166 if (invalidate) {
2167 // Invalidation trumps our writeback... discard here
2168 // Note: markInService will remove entry from writeback buffer.
2169 markInService(wb_entry);
2170 delete wb_pkt;
2171 }
2172 }
2173
2174 // If this was a shared writeback, there may still be
2175 // other shared copies above that require invalidation.
2176 // We could be more selective and return here if the
2177 // request is non-exclusive or if the writeback is
2178 // exclusive.
2179 uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false);
2180
2181 // Override what we did when we first saw the snoop, as we now
2182 // also have the cost of the upwards snoops to account for
2183 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay +
2184 lookupLatency * clockPeriod());
2185}
2186
2187bool
2188Cache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2189{
2190 // Express snoop responses from master to slave, e.g., from L1 to L2
2191 cache->recvTimingSnoopResp(pkt);
2192 return true;
2193}
2194
2195Tick
2196Cache::recvAtomicSnoop(PacketPtr pkt)
2197{
2198 // Snoops shouldn't happen when bypassing caches
2199 assert(!system->bypassCaches());
2200
2201 // no need to snoop requests that are not in range.
2202 if (!inRange(pkt->getAddr())) {
2203 return 0;
2204 }
2205
2206 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
2207 uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false);
2208 return snoop_delay + lookupLatency * clockPeriod();
2209}
2210
2211
2212QueueEntry*
2213Cache::getNextQueueEntry()
2214{
2215 // Check both MSHR queue and write buffer for potential requests,
2216 // note that null does not mean there is no request, it could
2217 // simply be that it is not ready
2218 MSHR *miss_mshr = mshrQueue.getNext();
2219 WriteQueueEntry *wq_entry = writeBuffer.getNext();
2220
2221 // If we got a write buffer request ready, first priority is a
2222 // full write buffer, otherwise we favour the miss requests
2223 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
2224 // need to search MSHR queue for conflicting earlier miss.
2225 MSHR *conflict_mshr =
2226 mshrQueue.findPending(wq_entry->blkAddr,
2227 wq_entry->isSecure);
2228
2229 if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
2230 // Service misses in order until conflict is cleared.
2231 return conflict_mshr;
2232
2233 // @todo Note that we ignore the ready time of the conflict here
2234 }
2235
2236 // No conflicts; issue write
2237 return wq_entry;
2238 } else if (miss_mshr) {
2239 // need to check for conflicting earlier writeback
2240 WriteQueueEntry *conflict_mshr =
2241 writeBuffer.findPending(miss_mshr->blkAddr,
2242 miss_mshr->isSecure);
2243 if (conflict_mshr) {
2244 // not sure why we don't check order here... it was in the
2245 // original code but commented out.
2246
2247 // The only way this happens is if we are
2248 // doing a write and we didn't have permissions
2249 // then subsequently saw a writeback (owned got evicted)
2250 // We need to make sure to perform the writeback first
2251 // To preserve the dirty data, then we can issue the write
2252
2253 // should we return wq_entry here instead? I.e. do we
2254 // have to flush writes in order? I don't think so... not
2255 // for Alpha anyway. Maybe for x86?
2256 return conflict_mshr;
2257
2258 // @todo Note that we ignore the ready time of the conflict here
2259 }
2260
2261 // No conflicts; issue read
2262 return miss_mshr;
2263 }
2264
2265 // fall through... no pending requests. Try a prefetch.
2266 assert(!miss_mshr && !wq_entry);
2267 if (prefetcher && mshrQueue.canPrefetch()) {
2268 // If we have a miss queue slot, we can try a prefetch
2269 PacketPtr pkt = prefetcher->getPacket();
2270 if (pkt) {
2271 Addr pf_addr = blockAlign(pkt->getAddr());
2272 if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
2273 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
2274 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
2275 // Update statistic on number of prefetches issued
2276 // (hwpf_mshr_misses)
2277 assert(pkt->req->masterId() < system->maxMasters());
2278 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
2279
2280 // allocate an MSHR and return it, note
2281 // that we send the packet straight away, so do not
2282 // schedule the send
2283 return allocateMissBuffer(pkt, curTick(), false);
2284 } else {
2285 // free the request and packet
2286 delete pkt->req;
2287 delete pkt;
2288 }
2289 }
2290 }
2291
2292 return nullptr;
2293}
2294
2295bool
2296Cache::isCachedAbove(PacketPtr pkt, bool is_timing) const
2297{
2298 if (!forwardSnoops)
2299 return false;
2300 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
2301 // Writeback snoops into upper level caches to check for copies of the
2302 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
2303 // packet, the cache can inform the crossbar below of presence or absence
2304 // of the block.
2305 if (is_timing) {
2306 Packet snoop_pkt(pkt, true, false);
2307 snoop_pkt.setExpressSnoop();
2308 // Assert that packet is either Writeback or CleanEvict and not a
2309 // prefetch request because prefetch requests need an MSHR and may
2310 // generate a snoop response.
2311 assert(pkt->isEviction());
| 1743 // No replaceable block or a mostly exclusive
1744 // cache... just use temporary storage to complete the
1745 // current request and then get rid of it
1746 assert(!tempBlock->isValid());
1747 blk = tempBlock;
1748 tempBlock->set = tags->extractSet(addr);
1749 tempBlock->tag = tags->extractTag(addr);
1750 // @todo: set security state as well...
1751 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
1752 is_secure ? "s" : "ns");
1753 } else {
1754 tags->insertBlock(pkt, blk);
1755 }
1756
1757 // we should never be overwriting a valid block
1758 assert(!blk->isValid());
1759 } else {
1760 // existing block... probably an upgrade
1761 assert(blk->tag == tags->extractTag(addr));
1762 // either we're getting new data or the block should already be valid
1763 assert(pkt->hasData() || blk->isValid());
1764 // don't clear block status... if block is already dirty we
1765 // don't want to lose that
1766 }
1767
1768 if (is_secure)
1769 blk->status |= BlkSecure;
1770 blk->status |= BlkValid | BlkReadable;
1771
1772 // sanity check for whole-line writes, which should always be
1773 // marked as writable as part of the fill, and then later marked
1774 // dirty as part of satisfyCpuSideRequest
1775 if (pkt->cmd == MemCmd::WriteLineReq) {
1776 assert(!pkt->hasSharers());
1777 // at the moment other caches do not respond to the
1778 // invalidation requests corresponding to a whole-line write
1779 assert(!pkt->cacheResponding());
1780 }
1781
1782 // here we deal with setting the appropriate state of the line,
1783 // and we start by looking at the hasSharers flag, and ignore the
1784 // cacheResponding flag (normally signalling dirty data) if the
1785 // packet has sharers, thus the line is never allocated as Owned
1786 // (dirty but not writable), and always ends up being either
1787 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1788 // for more details
1789 if (!pkt->hasSharers()) {
1790 // we could get a writable line from memory (rather than a
1791 // cache) even in a read-only cache, note that we set this bit
1792 // even for a read-only cache, possibly revisit this decision
1793 blk->status |= BlkWritable;
1794
1795 // check if we got this via cache-to-cache transfer (i.e., from a
1796 // cache that had the block in Modified or Owned state)
1797 if (pkt->cacheResponding()) {
1798 // we got the block in Modified state, and invalidated the
1799 // owners copy
1800 blk->status |= BlkDirty;
1801
1802 chatty_assert(!isReadOnly, "Should never see dirty snoop response "
1803 "in read-only cache %s\n", name());
1804 }
1805 }
1806
1807 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
1808 addr, is_secure ? "s" : "ns", old_state, blk->print());
1809
1810 // if we got new data, copy it in (checking for a read response
1811 // and a response that has data is the same in the end)
1812 if (pkt->isRead()) {
1813 // sanity checks
1814 assert(pkt->hasData());
1815 assert(pkt->getSize() == blkSize);
1816
1817 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize);
1818 }
1819 // We pay for fillLatency here.
1820 blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1821 pkt->payloadDelay;
1822
1823 return blk;
1824}
1825
1826
1827/////////////////////////////////////////////////////
1828//
1829// Snoop path: requests coming in from the memory side
1830//
1831/////////////////////////////////////////////////////
1832
1833void
1834Cache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
1835 bool already_copied, bool pending_inval)
1836{
1837 // sanity check
1838 assert(req_pkt->isRequest());
1839 assert(req_pkt->needsResponse());
1840
1841 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
1842 req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize());
1843 // timing-mode snoop responses require a new packet, unless we
1844 // already made a copy...
1845 PacketPtr pkt = req_pkt;
1846 if (!already_copied)
1847 // do not clear flags, and allocate space for data if the
1848 // packet needs it (the only packets that carry data are read
1849 // responses)
1850 pkt = new Packet(req_pkt, false, req_pkt->isRead());
1851
1852 assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() ||
1853 pkt->hasSharers());
1854 pkt->makeTimingResponse();
1855 if (pkt->isRead()) {
1856 pkt->setDataFromBlock(blk_data, blkSize);
1857 }
1858 if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
1859 // Assume we defer a response to a read from a far-away cache
1860 // A, then later defer a ReadExcl from a cache B on the same
1861 // bus as us. We'll assert cacheResponding in both cases, but
1862 // in the latter case cacheResponding will keep the
1863 // invalidation from reaching cache A. This special response
1864 // tells cache A that it gets the block to satisfy its read,
1865 // but must immediately invalidate it.
1866 pkt->cmd = MemCmd::ReadRespWithInvalidate;
1867 }
1868 // Here we consider forward_time, paying for just forward latency and
1869 // also charging the delay provided by the xbar.
1870 // forward_time is used as send_time in next allocateWriteBuffer().
1871 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1872 // Here we reset the timing of the packet.
1873 pkt->headerDelay = pkt->payloadDelay = 0;
1874 DPRINTF(CacheVerbose,
1875 "%s created response: %s addr %#llx size %d tick: %lu\n",
1876 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1877 forward_time);
1878 memSidePort->schedTimingSnoopResp(pkt, forward_time, true);
1879}
1880
1881uint32_t
1882Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
1883 bool is_deferred, bool pending_inval)
1884{
1885 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__,
1886 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1887 // deferred snoops can only happen in timing mode
1888 assert(!(is_deferred && !is_timing));
1889 // pending_inval only makes sense on deferred snoops
1890 assert(!(pending_inval && !is_deferred));
1891 assert(pkt->isRequest());
1892
1893 // the packet may get modified if we or a forwarded snooper
1894 // responds in atomic mode, so remember a few things about the
1895 // original packet up front
1896 bool invalidate = pkt->isInvalidate();
1897 bool M5_VAR_USED needs_writable = pkt->needsWritable();
1898
1899 // at the moment we could get an uncacheable write which does not
1900 // have the invalidate flag, and we need a suitable way of dealing
1901 // with this case
1902 panic_if(invalidate && pkt->req->isUncacheable(),
1903 "%s got an invalidating uncacheable snoop request %s to %#llx",
1904 name(), pkt->cmdString(), pkt->getAddr());
1905
1906 uint32_t snoop_delay = 0;
1907
1908 if (forwardSnoops) {
1909 // first propagate snoop upward to see if anyone above us wants to
1910 // handle it. save & restore packet src since it will get
1911 // rewritten to be relative to cpu-side bus (if any)
1912 bool alreadyResponded = pkt->cacheResponding();
1913 if (is_timing) {
1914 // copy the packet so that we can clear any flags before
1915 // forwarding it upwards, we also allocate data (passing
1916 // the pointer along in case of static data), in case
1917 // there is a snoop hit in upper levels
1918 Packet snoopPkt(pkt, true, true);
1919 snoopPkt.setExpressSnoop();
1920 // the snoop packet does not need to wait any additional
1921 // time
1922 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
1923 cpuSidePort->sendTimingSnoopReq(&snoopPkt);
1924
1925 // add the header delay (including crossbar and snoop
1926 // delays) of the upward snoop to the snoop delay for this
1927 // cache
1928 snoop_delay += snoopPkt.headerDelay;
1929
1930 if (snoopPkt.cacheResponding()) {
1931 // cache-to-cache response from some upper cache
1932 assert(!alreadyResponded);
1933 pkt->setCacheResponding();
1934 }
1935 // upstream cache has the block, or has an outstanding
1936 // MSHR, pass the flag on
1937 if (snoopPkt.hasSharers()) {
1938 pkt->setHasSharers();
1939 }
1940 // If this request is a prefetch or clean evict and an upper level
1941 // signals block present, make sure to propagate the block
1942 // presence to the requester.
1943 if (snoopPkt.isBlockCached()) {
1944 pkt->setBlockCached();
1945 }
1946 } else {
1947 cpuSidePort->sendAtomicSnoop(pkt);
1948 if (!alreadyResponded && pkt->cacheResponding()) {
1949 // cache-to-cache response from some upper cache:
1950 // forward response to original requester
1951 assert(pkt->isResponse());
1952 }
1953 }
1954 }
1955
1956 if (!blk || !blk->isValid()) {
1957 DPRINTF(CacheVerbose, "%s snoop miss for %s addr %#llx size %d\n",
1958 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1959 return snoop_delay;
1960 } else {
1961 DPRINTF(Cache, "%s snoop hit for %s addr %#llx size %d, "
1962 "old state is %s\n", __func__, pkt->cmdString(),
1963 pkt->getAddr(), pkt->getSize(), blk->print());
1964 }
1965
1966 chatty_assert(!(isReadOnly && blk->isDirty()),
1967 "Should never have a dirty block in a read-only cache %s\n",
1968 name());
1969
1970 // We may end up modifying both the block state and the packet (if
1971 // we respond in atomic mode), so just figure out what to do now
1972 // and then do it later. If we find dirty data while snooping for
1973 // an invalidate, we don't need to send a response. The
1974 // invalidation itself is taken care of below.
1975 bool respond = blk->isDirty() && pkt->needsResponse() &&
1976 pkt->cmd != MemCmd::InvalidateReq;
1977 bool have_writable = blk->isWritable();
1978
1979 // Invalidate any prefetch's from below that would strip write permissions
1980 // MemCmd::HardPFReq is only observed by upstream caches. After missing
1981 // above and in it's own cache, a new MemCmd::ReadReq is created that
1982 // downstream caches observe.
1983 if (pkt->mustCheckAbove()) {
1984 DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s "
1985 "from lower cache\n", pkt->getAddr(), pkt->cmdString());
1986 pkt->setBlockCached();
1987 return snoop_delay;
1988 }
1989
1990 if (pkt->isRead() && !invalidate) {
1991 // reading without requiring the line in a writable state
1992 assert(!needs_writable);
1993 pkt->setHasSharers();
1994
1995 // if the requesting packet is uncacheable, retain the line in
1996 // the current state, otherwhise unset the writable flag,
1997 // which means we go from Modified to Owned (and will respond
1998 // below), remain in Owned (and will respond below), from
1999 // Exclusive to Shared, or remain in Shared
2000 if (!pkt->req->isUncacheable())
2001 blk->status &= ~BlkWritable;
2002 }
2003
2004 if (respond) {
2005 // prevent anyone else from responding, cache as well as
2006 // memory, and also prevent any memory from even seeing the
2007 // request
2008 pkt->setCacheResponding();
2009 if (have_writable) {
2010 // inform the cache hierarchy that this cache had the line
2011 // in the Modified state so that we avoid unnecessary
2012 // invalidations (see Packet::setResponderHadWritable)
2013 pkt->setResponderHadWritable();
2014
2015 // in the case of an uncacheable request there is no point
2016 // in setting the responderHadWritable flag, but since the
2017 // recipient does not care there is no harm in doing so
2018 } else {
2019 // if the packet has needsWritable set we invalidate our
2020 // copy below and all other copies will be invalidates
2021 // through express snoops, and if needsWritable is not set
2022 // we already called setHasSharers above
2023 }
2024
2025 // if we are returning a writable and dirty (Modified) line,
2026 // we should be invalidating the line
2027 panic_if(!invalidate && !pkt->hasSharers(),
2028 "%s is passing a Modified line through %s to %#llx, "
2029 "but keeping the block",
2030 name(), pkt->cmdString(), pkt->getAddr());
2031
2032 if (is_timing) {
2033 doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
2034 } else {
2035 pkt->makeAtomicResponse();
2036 // packets such as upgrades do not actually have any data
2037 // payload
2038 if (pkt->hasData())
2039 pkt->setDataFromBlock(blk->data, blkSize);
2040 }
2041 }
2042
2043 if (!respond && is_timing && is_deferred) {
2044 // if it's a deferred timing snoop to which we are not
2045 // responding, then we've made a copy of both the request and
2046 // the packet, delete them here
2047 assert(pkt->needsResponse());
2048 delete pkt->req;
2049 delete pkt;
2050 }
2051
2052 // Do this last in case it deallocates block data or something
2053 // like that
2054 if (invalidate) {
2055 invalidateBlock(blk);
2056 }
2057
2058 DPRINTF(Cache, "new state is %s\n", blk->print());
2059
2060 return snoop_delay;
2061}
2062
2063
2064void
2065Cache::recvTimingSnoopReq(PacketPtr pkt)
2066{
2067 DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__,
2068 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
2069
2070 // Snoops shouldn't happen when bypassing caches
2071 assert(!system->bypassCaches());
2072
2073 // no need to snoop requests that are not in range
2074 if (!inRange(pkt->getAddr())) {
2075 return;
2076 }
2077
2078 bool is_secure = pkt->isSecure();
2079 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
2080
2081 Addr blk_addr = blockAlign(pkt->getAddr());
2082 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
2083
2084 // Update the latency cost of the snoop so that the crossbar can
2085 // account for it. Do not overwrite what other neighbouring caches
2086 // have already done, rather take the maximum. The update is
2087 // tentative, for cases where we return before an upward snoop
2088 // happens below.
2089 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay,
2090 lookupLatency * clockPeriod());
2091
2092 // Inform request(Prefetch, CleanEvict or Writeback) from below of
2093 // MSHR hit, set setBlockCached.
2094 if (mshr && pkt->mustCheckAbove()) {
2095 DPRINTF(Cache, "Setting block cached for %s from"
2096 "lower cache on mshr hit %#x\n",
2097 pkt->cmdString(), pkt->getAddr());
2098 pkt->setBlockCached();
2099 return;
2100 }
2101
2102 // Let the MSHR itself track the snoop and decide whether we want
2103 // to go ahead and do the regular cache snoop
2104 if (mshr && mshr->handleSnoop(pkt, order++)) {
2105 DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)."
2106 "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns",
2107 mshr->print());
2108
2109 if (mshr->getNumTargets() > numTarget)
2110 warn("allocating bonus target for snoop"); //handle later
2111 return;
2112 }
2113
2114 //We also need to check the writeback buffers and handle those
2115 WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure);
2116 if (wb_entry) {
2117 DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n",
2118 pkt->getAddr(), is_secure ? "s" : "ns");
2119 // Expect to see only Writebacks and/or CleanEvicts here, both of
2120 // which should not be generated for uncacheable data.
2121 assert(!wb_entry->isUncacheable());
2122 // There should only be a single request responsible for generating
2123 // Writebacks/CleanEvicts.
2124 assert(wb_entry->getNumTargets() == 1);
2125 PacketPtr wb_pkt = wb_entry->getTarget()->pkt;
2126 assert(wb_pkt->isEviction());
2127
2128 if (pkt->isEviction()) {
2129 // if the block is found in the write queue, set the BLOCK_CACHED
2130 // flag for Writeback/CleanEvict snoop. On return the snoop will
2131 // propagate the BLOCK_CACHED flag in Writeback packets and prevent
2132 // any CleanEvicts from travelling down the memory hierarchy.
2133 pkt->setBlockCached();
2134 DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit"
2135 " %#x\n", pkt->cmdString(), pkt->getAddr());
2136 return;
2137 }
2138
2139 // conceptually writebacks are no different to other blocks in
2140 // this cache, so the behaviour is modelled after handleSnoop,
2141 // the difference being that instead of querying the block
2142 // state to determine if it is dirty and writable, we use the
2143 // command and fields of the writeback packet
2144 bool respond = wb_pkt->cmd == MemCmd::WritebackDirty &&
2145 pkt->needsResponse() && pkt->cmd != MemCmd::InvalidateReq;
2146 bool have_writable = !wb_pkt->hasSharers();
2147 bool invalidate = pkt->isInvalidate();
2148
2149 if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) {
2150 assert(!pkt->needsWritable());
2151 pkt->setHasSharers();
2152 wb_pkt->setHasSharers();
2153 }
2154
2155 if (respond) {
2156 pkt->setCacheResponding();
2157
2158 if (have_writable) {
2159 pkt->setResponderHadWritable();
2160 }
2161
2162 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(),
2163 false, false);
2164 }
2165
2166 if (invalidate) {
2167 // Invalidation trumps our writeback... discard here
2168 // Note: markInService will remove entry from writeback buffer.
2169 markInService(wb_entry);
2170 delete wb_pkt;
2171 }
2172 }
2173
2174 // If this was a shared writeback, there may still be
2175 // other shared copies above that require invalidation.
2176 // We could be more selective and return here if the
2177 // request is non-exclusive or if the writeback is
2178 // exclusive.
2179 uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false);
2180
2181 // Override what we did when we first saw the snoop, as we now
2182 // also have the cost of the upwards snoops to account for
2183 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay +
2184 lookupLatency * clockPeriod());
2185}
2186
2187bool
2188Cache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2189{
2190 // Express snoop responses from master to slave, e.g., from L1 to L2
2191 cache->recvTimingSnoopResp(pkt);
2192 return true;
2193}
2194
2195Tick
2196Cache::recvAtomicSnoop(PacketPtr pkt)
2197{
2198 // Snoops shouldn't happen when bypassing caches
2199 assert(!system->bypassCaches());
2200
2201 // no need to snoop requests that are not in range.
2202 if (!inRange(pkt->getAddr())) {
2203 return 0;
2204 }
2205
2206 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
2207 uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false);
2208 return snoop_delay + lookupLatency * clockPeriod();
2209}
2210
2211
2212QueueEntry*
2213Cache::getNextQueueEntry()
2214{
2215 // Check both MSHR queue and write buffer for potential requests,
2216 // note that null does not mean there is no request, it could
2217 // simply be that it is not ready
2218 MSHR *miss_mshr = mshrQueue.getNext();
2219 WriteQueueEntry *wq_entry = writeBuffer.getNext();
2220
2221 // If we got a write buffer request ready, first priority is a
2222 // full write buffer, otherwise we favour the miss requests
2223 if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
2224 // need to search MSHR queue for conflicting earlier miss.
2225 MSHR *conflict_mshr =
2226 mshrQueue.findPending(wq_entry->blkAddr,
2227 wq_entry->isSecure);
2228
2229 if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
2230 // Service misses in order until conflict is cleared.
2231 return conflict_mshr;
2232
2233 // @todo Note that we ignore the ready time of the conflict here
2234 }
2235
2236 // No conflicts; issue write
2237 return wq_entry;
2238 } else if (miss_mshr) {
2239 // need to check for conflicting earlier writeback
2240 WriteQueueEntry *conflict_mshr =
2241 writeBuffer.findPending(miss_mshr->blkAddr,
2242 miss_mshr->isSecure);
2243 if (conflict_mshr) {
2244 // not sure why we don't check order here... it was in the
2245 // original code but commented out.
2246
2247 // The only way this happens is if we are
2248 // doing a write and we didn't have permissions
2249 // then subsequently saw a writeback (owned got evicted)
2250 // We need to make sure to perform the writeback first
2251 // To preserve the dirty data, then we can issue the write
2252
2253 // should we return wq_entry here instead? I.e. do we
2254 // have to flush writes in order? I don't think so... not
2255 // for Alpha anyway. Maybe for x86?
2256 return conflict_mshr;
2257
2258 // @todo Note that we ignore the ready time of the conflict here
2259 }
2260
2261 // No conflicts; issue read
2262 return miss_mshr;
2263 }
2264
2265 // fall through... no pending requests. Try a prefetch.
2266 assert(!miss_mshr && !wq_entry);
2267 if (prefetcher && mshrQueue.canPrefetch()) {
2268 // If we have a miss queue slot, we can try a prefetch
2269 PacketPtr pkt = prefetcher->getPacket();
2270 if (pkt) {
2271 Addr pf_addr = blockAlign(pkt->getAddr());
2272 if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
2273 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
2274 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
2275 // Update statistic on number of prefetches issued
2276 // (hwpf_mshr_misses)
2277 assert(pkt->req->masterId() < system->maxMasters());
2278 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
2279
2280 // allocate an MSHR and return it, note
2281 // that we send the packet straight away, so do not
2282 // schedule the send
2283 return allocateMissBuffer(pkt, curTick(), false);
2284 } else {
2285 // free the request and packet
2286 delete pkt->req;
2287 delete pkt;
2288 }
2289 }
2290 }
2291
2292 return nullptr;
2293}
2294
2295bool
2296Cache::isCachedAbove(PacketPtr pkt, bool is_timing) const
2297{
2298 if (!forwardSnoops)
2299 return false;
2300 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
2301 // Writeback snoops into upper level caches to check for copies of the
2302 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
2303 // packet, the cache can inform the crossbar below of presence or absence
2304 // of the block.
2305 if (is_timing) {
2306 Packet snoop_pkt(pkt, true, false);
2307 snoop_pkt.setExpressSnoop();
2308 // Assert that packet is either Writeback or CleanEvict and not a
2309 // prefetch request because prefetch requests need an MSHR and may
2310 // generate a snoop response.
2311 assert(pkt->isEviction());
|
2312 snoop_pkt.senderState = NULL;
| 2312 snoop_pkt.senderState = nullptr;
|
2313 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2314 // Writeback/CleanEvict snoops do not generate a snoop response.
2315 assert(!(snoop_pkt.cacheResponding()));
2316 return snoop_pkt.isBlockCached();
2317 } else {
2318 cpuSidePort->sendAtomicSnoop(pkt);
2319 return pkt->isBlockCached();
2320 }
2321}
2322
2323Tick
2324Cache::nextQueueReadyTime() const
2325{
2326 Tick nextReady = std::min(mshrQueue.nextReadyTime(),
2327 writeBuffer.nextReadyTime());
2328
2329 // Don't signal prefetch ready time if no MSHRs available
2330 // Will signal once enoguh MSHRs are deallocated
2331 if (prefetcher && mshrQueue.canPrefetch()) {
2332 nextReady = std::min(nextReady,
2333 prefetcher->nextPrefetchReadyTime());
2334 }
2335
2336 return nextReady;
2337}
2338
2339bool
2340Cache::sendMSHRQueuePacket(MSHR* mshr)
2341{
2342 assert(mshr);
2343
2344 // use request from 1st target
2345 PacketPtr tgt_pkt = mshr->getTarget()->pkt;
2346
2347 DPRINTF(Cache, "%s MSHR %s for addr %#llx size %d\n", __func__,
2348 tgt_pkt->cmdString(), tgt_pkt->getAddr(),
2349 tgt_pkt->getSize());
2350
2351 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
2352
2353 if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) {
2354 // we should never have hardware prefetches to allocated
2355 // blocks
| 2313 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2314 // Writeback/CleanEvict snoops do not generate a snoop response.
2315 assert(!(snoop_pkt.cacheResponding()));
2316 return snoop_pkt.isBlockCached();
2317 } else {
2318 cpuSidePort->sendAtomicSnoop(pkt);
2319 return pkt->isBlockCached();
2320 }
2321}
2322
2323Tick
2324Cache::nextQueueReadyTime() const
2325{
2326 Tick nextReady = std::min(mshrQueue.nextReadyTime(),
2327 writeBuffer.nextReadyTime());
2328
2329 // Don't signal prefetch ready time if no MSHRs available
2330 // Will signal once enoguh MSHRs are deallocated
2331 if (prefetcher && mshrQueue.canPrefetch()) {
2332 nextReady = std::min(nextReady,
2333 prefetcher->nextPrefetchReadyTime());
2334 }
2335
2336 return nextReady;
2337}
2338
2339bool
2340Cache::sendMSHRQueuePacket(MSHR* mshr)
2341{
2342 assert(mshr);
2343
2344 // use request from 1st target
2345 PacketPtr tgt_pkt = mshr->getTarget()->pkt;
2346
2347 DPRINTF(Cache, "%s MSHR %s for addr %#llx size %d\n", __func__,
2348 tgt_pkt->cmdString(), tgt_pkt->getAddr(),
2349 tgt_pkt->getSize());
2350
2351 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
2352
2353 if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) {
2354 // we should never have hardware prefetches to allocated
2355 // blocks
|
2356 assert(blk == NULL);
| 2356 assert(blk == nullptr);
|
2357
2358 // We need to check the caches above us to verify that
2359 // they don't have a copy of this block in the dirty state
2360 // at the moment. Without this check we could get a stale
2361 // copy from memory that might get used in place of the
2362 // dirty one.
2363 Packet snoop_pkt(tgt_pkt, true, false);
2364 snoop_pkt.setExpressSnoop();
2365 // We are sending this packet upwards, but if it hits we will
2366 // get a snoop response that we end up treating just like a
2367 // normal response, hence it needs the MSHR as its sender
2368 // state
2369 snoop_pkt.senderState = mshr;
2370 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2371
2372 // Check to see if the prefetch was squashed by an upper cache (to
2373 // prevent us from grabbing the line) or if a Check to see if a
2374 // writeback arrived between the time the prefetch was placed in
2375 // the MSHRs and when it was selected to be sent or if the
2376 // prefetch was squashed by an upper cache.
2377
2378 // It is important to check cacheResponding before
2379 // prefetchSquashed. If another cache has committed to
2380 // responding, it will be sending a dirty response which will
2381 // arrive at the MSHR allocated for this request. Checking the
2382 // prefetchSquash first may result in the MSHR being
2383 // prematurely deallocated.
2384 if (snoop_pkt.cacheResponding()) {
2385 auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req);
2386 assert(r.second);
2387
2388 // if we are getting a snoop response with no sharers it
2389 // will be allocated as Modified
2390 bool pending_modified_resp = !snoop_pkt.hasSharers();
2391 markInService(mshr, pending_modified_resp);
2392
2393 DPRINTF(Cache, "Upward snoop of prefetch for addr"
2394 " %#x (%s) hit\n",
2395 tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns");
2396 return false;
2397 }
2398
2399 if (snoop_pkt.isBlockCached()) {
2400 DPRINTF(Cache, "Block present, prefetch squashed by cache. "
2401 "Deallocating mshr target %#x.\n",
2402 mshr->blkAddr);
2403
2404 // Deallocate the mshr target
2405 if (mshrQueue.forceDeallocateTarget(mshr)) {
2406 // Clear block if this deallocation resulted freed an
2407 // mshr when all had previously been utilized
2408 clearBlocked(Blocked_NoMSHRs);
2409 }
2410 return false;
2411 }
2412 }
2413
2414 // either a prefetch that is not present upstream, or a normal
2415 // MSHR request, proceed to get the packet to send downstream
2416 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
2417
| 2357
2358 // We need to check the caches above us to verify that
2359 // they don't have a copy of this block in the dirty state
2360 // at the moment. Without this check we could get a stale
2361 // copy from memory that might get used in place of the
2362 // dirty one.
2363 Packet snoop_pkt(tgt_pkt, true, false);
2364 snoop_pkt.setExpressSnoop();
2365 // We are sending this packet upwards, but if it hits we will
2366 // get a snoop response that we end up treating just like a
2367 // normal response, hence it needs the MSHR as its sender
2368 // state
2369 snoop_pkt.senderState = mshr;
2370 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2371
2372 // Check to see if the prefetch was squashed by an upper cache (to
2373 // prevent us from grabbing the line) or if a Check to see if a
2374 // writeback arrived between the time the prefetch was placed in
2375 // the MSHRs and when it was selected to be sent or if the
2376 // prefetch was squashed by an upper cache.
2377
2378 // It is important to check cacheResponding before
2379 // prefetchSquashed. If another cache has committed to
2380 // responding, it will be sending a dirty response which will
2381 // arrive at the MSHR allocated for this request. Checking the
2382 // prefetchSquash first may result in the MSHR being
2383 // prematurely deallocated.
2384 if (snoop_pkt.cacheResponding()) {
2385 auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req);
2386 assert(r.second);
2387
2388 // if we are getting a snoop response with no sharers it
2389 // will be allocated as Modified
2390 bool pending_modified_resp = !snoop_pkt.hasSharers();
2391 markInService(mshr, pending_modified_resp);
2392
2393 DPRINTF(Cache, "Upward snoop of prefetch for addr"
2394 " %#x (%s) hit\n",
2395 tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns");
2396 return false;
2397 }
2398
2399 if (snoop_pkt.isBlockCached()) {
2400 DPRINTF(Cache, "Block present, prefetch squashed by cache. "
2401 "Deallocating mshr target %#x.\n",
2402 mshr->blkAddr);
2403
2404 // Deallocate the mshr target
2405 if (mshrQueue.forceDeallocateTarget(mshr)) {
2406 // Clear block if this deallocation resulted freed an
2407 // mshr when all had previously been utilized
2408 clearBlocked(Blocked_NoMSHRs);
2409 }
2410 return false;
2411 }
2412 }
2413
2414 // either a prefetch that is not present upstream, or a normal
2415 // MSHR request, proceed to get the packet to send downstream
2416 PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
2417
|
2418 mshr->isForward = (pkt == NULL);
| 2418 mshr->isForward = (pkt == nullptr);
|
2419
2420 if (mshr->isForward) {
2421 // not a cache block request, but a response is expected
2422 // make copy of current packet to forward, keep current
2423 // copy for response handling
2424 pkt = new Packet(tgt_pkt, false, true);
2425 assert(!pkt->isWrite());
2426 }
2427
2428 // play it safe and append (rather than set) the sender state,
2429 // as forwarded packets may already have existing state
2430 pkt->pushSenderState(mshr);
2431
2432 if (!memSidePort->sendTimingReq(pkt)) {
2433 // we are awaiting a retry, but we
2434 // delete the packet and will be creating a new packet
2435 // when we get the opportunity
2436 delete pkt;
2437
2438 // note that we have now masked any requestBus and
2439 // schedSendEvent (we will wait for a retry before
2440 // doing anything), and this is so even if we do not
2441 // care about this packet and might override it before
2442 // it gets retried
2443 return true;
2444 } else {
2445 // As part of the call to sendTimingReq the packet is
2446 // forwarded to all neighbouring caches (and any caches
2447 // above them) as a snoop. Thus at this point we know if
2448 // any of the neighbouring caches are responding, and if
2449 // so, we know it is dirty, and we can determine if it is
2450 // being passed as Modified, making our MSHR the ordering
2451 // point
2452 bool pending_modified_resp = !pkt->hasSharers() &&
2453 pkt->cacheResponding();
2454 markInService(mshr, pending_modified_resp);
2455 return false;
2456 }
2457}
2458
2459bool
2460Cache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
2461{
2462 assert(wq_entry);
2463
2464 // always a single target for write queue entries
2465 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
2466
2467 DPRINTF(Cache, "%s write %s for addr %#llx size %d\n", __func__,
2468 tgt_pkt->cmdString(), tgt_pkt->getAddr(),
2469 tgt_pkt->getSize());
2470
2471 // forward as is, both for evictions and uncacheable writes
2472 if (!memSidePort->sendTimingReq(tgt_pkt)) {
2473 // note that we have now masked any requestBus and
2474 // schedSendEvent (we will wait for a retry before
2475 // doing anything), and this is so even if we do not
2476 // care about this packet and might override it before
2477 // it gets retried
2478 return true;
2479 } else {
2480 markInService(wq_entry);
2481 return false;
2482 }
2483}
2484
2485void
2486Cache::serialize(CheckpointOut &cp) const
2487{
2488 bool dirty(isDirty());
2489
2490 if (dirty) {
2491 warn("*** The cache still contains dirty data. ***\n");
2492 warn(" Make sure to drain the system using the correct flags.\n");
2493 warn(" This checkpoint will not restore correctly and dirty data "
2494 " in the cache will be lost!\n");
2495 }
2496
2497 // Since we don't checkpoint the data in the cache, any dirty data
2498 // will be lost when restoring from a checkpoint of a system that
2499 // wasn't drained properly. Flag the checkpoint as invalid if the
2500 // cache contains dirty data.
2501 bool bad_checkpoint(dirty);
2502 SERIALIZE_SCALAR(bad_checkpoint);
2503}
2504
2505void
2506Cache::unserialize(CheckpointIn &cp)
2507{
2508 bool bad_checkpoint;
2509 UNSERIALIZE_SCALAR(bad_checkpoint);
2510 if (bad_checkpoint) {
2511 fatal("Restoring from checkpoints with dirty caches is not supported "
2512 "in the classic memory system. Please remove any caches or "
2513 " drain them properly before taking checkpoints.\n");
2514 }
2515}
2516
2517///////////////
2518//
2519// CpuSidePort
2520//
2521///////////////
2522
2523AddrRangeList
2524Cache::CpuSidePort::getAddrRanges() const
2525{
2526 return cache->getAddrRanges();
2527}
2528
2529bool
2530Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2531{
2532 assert(!cache->system->bypassCaches());
2533
2534 bool success = false;
2535
2536 // always let express snoop packets through if even if blocked
2537 if (pkt->isExpressSnoop()) {
2538 // do not change the current retry state
2539 bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
2540 assert(bypass_success);
2541 return true;
2542 } else if (blocked || mustSendRetry) {
2543 // either already committed to send a retry, or blocked
2544 success = false;
2545 } else {
2546 // pass it on to the cache, and let the cache decide if we
2547 // have to retry or not
2548 success = cache->recvTimingReq(pkt);
2549 }
2550
2551 // remember if we have to retry
2552 mustSendRetry = !success;
2553 return success;
2554}
2555
2556Tick
2557Cache::CpuSidePort::recvAtomic(PacketPtr pkt)
2558{
2559 return cache->recvAtomic(pkt);
2560}
2561
2562void
2563Cache::CpuSidePort::recvFunctional(PacketPtr pkt)
2564{
2565 // functional request
2566 cache->functionalAccess(pkt, true);
2567}
2568
2569Cache::
2570CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
2571 const std::string &_label)
2572 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
2573{
2574}
2575
2576Cache*
2577CacheParams::create()
2578{
2579 assert(tags);
2580
2581 return new Cache(this);
2582}
2583///////////////
2584//
2585// MemSidePort
2586//
2587///////////////
2588
2589bool
2590Cache::MemSidePort::recvTimingResp(PacketPtr pkt)
2591{
2592 cache->recvTimingResp(pkt);
2593 return true;
2594}
2595
2596// Express snooping requests to memside port
2597void
2598Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2599{
2600 // handle snooping requests
2601 cache->recvTimingSnoopReq(pkt);
2602}
2603
2604Tick
2605Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2606{
2607 return cache->recvAtomicSnoop(pkt);
2608}
2609
2610void
2611Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2612{
2613 // functional snoop (note that in contrast to atomic we don't have
2614 // a specific functionalSnoop method, as they have the same
2615 // behaviour regardless)
2616 cache->functionalAccess(pkt, false);
2617}
2618
2619void
2620Cache::CacheReqPacketQueue::sendDeferredPacket()
2621{
2622 // sanity check
2623 assert(!waitingOnRetry);
2624
2625 // there should never be any deferred request packets in the
2626 // queue, instead we resly on the cache to provide the packets
2627 // from the MSHR queue or write queue
2628 assert(deferredPacketReadyTime() == MaxTick);
2629
2630 // check for request packets (requests & writebacks)
2631 QueueEntry* entry = cache.getNextQueueEntry();
2632
2633 if (!entry) {
2634 // can happen if e.g. we attempt a writeback and fail, but
2635 // before the retry, the writeback is eliminated because
2636 // we snoop another cache's ReadEx.
2637 } else {
2638 // let our snoop responses go first if there are responses to
2639 // the same addresses
2640 if (checkConflictingSnoop(entry->blkAddr)) {
2641 return;
2642 }
2643 waitingOnRetry = entry->sendPacket(cache);
2644 }
2645
2646 // if we succeeded and are not waiting for a retry, schedule the
2647 // next send considering when the next queue is ready, note that
2648 // snoop responses have their own packet queue and thus schedule
2649 // their own events
2650 if (!waitingOnRetry) {
2651 schedSendEvent(cache.nextQueueReadyTime());
2652 }
2653}
2654
2655Cache::
2656MemSidePort::MemSidePort(const std::string &_name, Cache *_cache,
2657 const std::string &_label)
2658 : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2659 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2660 _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2661{
2662}
| 2419
2420 if (mshr->isForward) {
2421 // not a cache block request, but a response is expected
2422 // make copy of current packet to forward, keep current
2423 // copy for response handling
2424 pkt = new Packet(tgt_pkt, false, true);
2425 assert(!pkt->isWrite());
2426 }
2427
2428 // play it safe and append (rather than set) the sender state,
2429 // as forwarded packets may already have existing state
2430 pkt->pushSenderState(mshr);
2431
2432 if (!memSidePort->sendTimingReq(pkt)) {
2433 // we are awaiting a retry, but we
2434 // delete the packet and will be creating a new packet
2435 // when we get the opportunity
2436 delete pkt;
2437
2438 // note that we have now masked any requestBus and
2439 // schedSendEvent (we will wait for a retry before
2440 // doing anything), and this is so even if we do not
2441 // care about this packet and might override it before
2442 // it gets retried
2443 return true;
2444 } else {
2445 // As part of the call to sendTimingReq the packet is
2446 // forwarded to all neighbouring caches (and any caches
2447 // above them) as a snoop. Thus at this point we know if
2448 // any of the neighbouring caches are responding, and if
2449 // so, we know it is dirty, and we can determine if it is
2450 // being passed as Modified, making our MSHR the ordering
2451 // point
2452 bool pending_modified_resp = !pkt->hasSharers() &&
2453 pkt->cacheResponding();
2454 markInService(mshr, pending_modified_resp);
2455 return false;
2456 }
2457}
2458
2459bool
2460Cache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
2461{
2462 assert(wq_entry);
2463
2464 // always a single target for write queue entries
2465 PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
2466
2467 DPRINTF(Cache, "%s write %s for addr %#llx size %d\n", __func__,
2468 tgt_pkt->cmdString(), tgt_pkt->getAddr(),
2469 tgt_pkt->getSize());
2470
2471 // forward as is, both for evictions and uncacheable writes
2472 if (!memSidePort->sendTimingReq(tgt_pkt)) {
2473 // note that we have now masked any requestBus and
2474 // schedSendEvent (we will wait for a retry before
2475 // doing anything), and this is so even if we do not
2476 // care about this packet and might override it before
2477 // it gets retried
2478 return true;
2479 } else {
2480 markInService(wq_entry);
2481 return false;
2482 }
2483}
2484
2485void
2486Cache::serialize(CheckpointOut &cp) const
2487{
2488 bool dirty(isDirty());
2489
2490 if (dirty) {
2491 warn("*** The cache still contains dirty data. ***\n");
2492 warn(" Make sure to drain the system using the correct flags.\n");
2493 warn(" This checkpoint will not restore correctly and dirty data "
2494 " in the cache will be lost!\n");
2495 }
2496
2497 // Since we don't checkpoint the data in the cache, any dirty data
2498 // will be lost when restoring from a checkpoint of a system that
2499 // wasn't drained properly. Flag the checkpoint as invalid if the
2500 // cache contains dirty data.
2501 bool bad_checkpoint(dirty);
2502 SERIALIZE_SCALAR(bad_checkpoint);
2503}
2504
2505void
2506Cache::unserialize(CheckpointIn &cp)
2507{
2508 bool bad_checkpoint;
2509 UNSERIALIZE_SCALAR(bad_checkpoint);
2510 if (bad_checkpoint) {
2511 fatal("Restoring from checkpoints with dirty caches is not supported "
2512 "in the classic memory system. Please remove any caches or "
2513 " drain them properly before taking checkpoints.\n");
2514 }
2515}
2516
2517///////////////
2518//
2519// CpuSidePort
2520//
2521///////////////
2522
2523AddrRangeList
2524Cache::CpuSidePort::getAddrRanges() const
2525{
2526 return cache->getAddrRanges();
2527}
2528
2529bool
2530Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2531{
2532 assert(!cache->system->bypassCaches());
2533
2534 bool success = false;
2535
2536 // always let express snoop packets through if even if blocked
2537 if (pkt->isExpressSnoop()) {
2538 // do not change the current retry state
2539 bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
2540 assert(bypass_success);
2541 return true;
2542 } else if (blocked || mustSendRetry) {
2543 // either already committed to send a retry, or blocked
2544 success = false;
2545 } else {
2546 // pass it on to the cache, and let the cache decide if we
2547 // have to retry or not
2548 success = cache->recvTimingReq(pkt);
2549 }
2550
2551 // remember if we have to retry
2552 mustSendRetry = !success;
2553 return success;
2554}
2555
2556Tick
2557Cache::CpuSidePort::recvAtomic(PacketPtr pkt)
2558{
2559 return cache->recvAtomic(pkt);
2560}
2561
2562void
2563Cache::CpuSidePort::recvFunctional(PacketPtr pkt)
2564{
2565 // functional request
2566 cache->functionalAccess(pkt, true);
2567}
2568
2569Cache::
2570CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
2571 const std::string &_label)
2572 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
2573{
2574}
2575
2576Cache*
2577CacheParams::create()
2578{
2579 assert(tags);
2580
2581 return new Cache(this);
2582}
2583///////////////
2584//
2585// MemSidePort
2586//
2587///////////////
2588
2589bool
2590Cache::MemSidePort::recvTimingResp(PacketPtr pkt)
2591{
2592 cache->recvTimingResp(pkt);
2593 return true;
2594}
2595
2596// Express snooping requests to memside port
2597void
2598Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2599{
2600 // handle snooping requests
2601 cache->recvTimingSnoopReq(pkt);
2602}
2603
2604Tick
2605Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2606{
2607 return cache->recvAtomicSnoop(pkt);
2608}
2609
2610void
2611Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2612{
2613 // functional snoop (note that in contrast to atomic we don't have
2614 // a specific functionalSnoop method, as they have the same
2615 // behaviour regardless)
2616 cache->functionalAccess(pkt, false);
2617}
2618
2619void
2620Cache::CacheReqPacketQueue::sendDeferredPacket()
2621{
2622 // sanity check
2623 assert(!waitingOnRetry);
2624
2625 // there should never be any deferred request packets in the
2626 // queue, instead we resly on the cache to provide the packets
2627 // from the MSHR queue or write queue
2628 assert(deferredPacketReadyTime() == MaxTick);
2629
2630 // check for request packets (requests & writebacks)
2631 QueueEntry* entry = cache.getNextQueueEntry();
2632
2633 if (!entry) {
2634 // can happen if e.g. we attempt a writeback and fail, but
2635 // before the retry, the writeback is eliminated because
2636 // we snoop another cache's ReadEx.
2637 } else {
2638 // let our snoop responses go first if there are responses to
2639 // the same addresses
2640 if (checkConflictingSnoop(entry->blkAddr)) {
2641 return;
2642 }
2643 waitingOnRetry = entry->sendPacket(cache);
2644 }
2645
2646 // if we succeeded and are not waiting for a retry, schedule the
2647 // next send considering when the next queue is ready, note that
2648 // snoop responses have their own packet queue and thus schedule
2649 // their own events
2650 if (!waitingOnRetry) {
2651 schedSendEvent(cache.nextQueueReadyTime());
2652 }
2653}
2654
2655Cache::
2656MemSidePort::MemSidePort(const std::string &_name, Cache *_cache,
2657 const std::string &_label)
2658 : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2659 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2660 _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2661{
2662}
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