1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Erik Hallnor
42 * Dave Greene
43 * Nathan Binkert
44 * Steve Reinhardt
45 * Ron Dreslinski
46 * Andreas Sandberg
47 */
48
49/**
50 * @file
51 * Cache definitions.
52 */
53
54#include "mem/cache/cache.hh"
55
56#include "base/misc.hh"
57#include "base/types.hh"
58#include "debug/Cache.hh"
59#include "debug/CachePort.hh"
60#include "debug/CacheTags.hh"
61#include "mem/cache/blk.hh"
62#include "mem/cache/mshr.hh"
63#include "mem/cache/prefetch/base.hh"
64#include "sim/sim_exit.hh"
65
66Cache::Cache(const CacheParams *p)
67 : BaseCache(p, p->system->cacheLineSize()),
68 tags(p->tags),
69 prefetcher(p->prefetcher),
70 doFastWrites(true),
71 prefetchOnAccess(p->prefetch_on_access),
72 clusivity(p->clusivity),
73 writebackClean(p->writeback_clean),
74 tempBlockWriteback(nullptr),
75 writebackTempBlockAtomicEvent(this, false,
76 EventBase::Delayed_Writeback_Pri)
77{
78 tempBlock = new CacheBlk();
79 tempBlock->data = new uint8_t[blkSize];
80
81 cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
82 "CpuSidePort");
83 memSidePort = new MemSidePort(p->name + ".mem_side", this,
84 "MemSidePort");
85
86 tags->setCache(this);
87 if (prefetcher)
88 prefetcher->setCache(this);
89}
90
91Cache::~Cache()
92{
93 delete [] tempBlock->data;
94 delete tempBlock;
95
96 delete cpuSidePort;
97 delete memSidePort;
98}
99
100void
101Cache::regStats()
102{
103 BaseCache::regStats();
104}
105
106void
107Cache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
108{
109 assert(pkt->isRequest());
110
111 uint64_t overwrite_val;
112 bool overwrite_mem;
113 uint64_t condition_val64;
114 uint32_t condition_val32;
115
116 int offset = tags->extractBlkOffset(pkt->getAddr());
117 uint8_t *blk_data = blk->data + offset;
118
119 assert(sizeof(uint64_t) >= pkt->getSize());
120
121 overwrite_mem = true;
122 // keep a copy of our possible write value, and copy what is at the
123 // memory address into the packet
124 pkt->writeData((uint8_t *)&overwrite_val);
125 pkt->setData(blk_data);
126
127 if (pkt->req->isCondSwap()) {
128 if (pkt->getSize() == sizeof(uint64_t)) {
129 condition_val64 = pkt->req->getExtraData();
130 overwrite_mem = !std::memcmp(&condition_val64, blk_data,
131 sizeof(uint64_t));
132 } else if (pkt->getSize() == sizeof(uint32_t)) {
133 condition_val32 = (uint32_t)pkt->req->getExtraData();
134 overwrite_mem = !std::memcmp(&condition_val32, blk_data,
135 sizeof(uint32_t));
136 } else
137 panic("Invalid size for conditional read/write\n");
138 }
139
140 if (overwrite_mem) {
141 std::memcpy(blk_data, &overwrite_val, pkt->getSize());
142 blk->status |= BlkDirty;
143 }
144}
145
146
147void
148Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
149 bool deferred_response, bool pending_downgrade)
150{
151 assert(pkt->isRequest());
152
153 assert(blk && blk->isValid());
154 // Occasionally this is not true... if we are a lower-level cache
155 // satisfying a string of Read and ReadEx requests from
156 // upper-level caches, a Read will mark the block as shared but we
157 // can satisfy a following ReadEx anyway since we can rely on the
158 // Read requester(s) to have buffered the ReadEx snoop and to
159 // invalidate their blocks after receiving them.
160 // assert(!pkt->needsWritable() || blk->isWritable());
161 assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
162
163 // Check RMW operations first since both isRead() and
164 // isWrite() will be true for them
165 if (pkt->cmd == MemCmd::SwapReq) {
166 cmpAndSwap(blk, pkt);
167 } else if (pkt->isWrite()) {
168 // we have the block in a writable state and can go ahead,
169 // note that the line may be also be considered writable in
170 // downstream caches along the path to memory, but always
171 // Exclusive, and never Modified
172 assert(blk->isWritable());
173 // Write or WriteLine at the first cache with block in writable state
174 if (blk->checkWrite(pkt)) {
175 pkt->writeDataToBlock(blk->data, blkSize);
176 }
177 // Always mark the line as dirty (and thus transition to the
178 // Modified state) even if we are a failed StoreCond so we
179 // supply data to any snoops that have appended themselves to
180 // this cache before knowing the store will fail.
181 blk->status |= BlkDirty;
182 DPRINTF(Cache, "%s for %s addr %#llx size %d (write)\n", __func__,
183 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
184 } else if (pkt->isRead()) {
185 if (pkt->isLLSC()) {
186 blk->trackLoadLocked(pkt);
187 }
188 pkt->setDataFromBlock(blk->data, blkSize);
189 // determine if this read is from a (coherent) cache, or not
190 // by looking at the command type; we could potentially add a
191 // packet attribute such as 'FromCache' to make this check a
192 // bit cleaner
193 if (pkt->cmd == MemCmd::ReadExReq ||
194 pkt->cmd == MemCmd::ReadSharedReq ||
195 pkt->cmd == MemCmd::ReadCleanReq ||
196 pkt->cmd == MemCmd::SCUpgradeFailReq) {
197 assert(pkt->getSize() == blkSize);
198 // special handling for coherent block requests from
199 // upper-level caches
200 if (pkt->needsWritable()) {
201 // sanity check
202 assert(pkt->cmd == MemCmd::ReadExReq ||
203 pkt->cmd == MemCmd::SCUpgradeFailReq);
204
205 // if we have a dirty copy, make sure the recipient
206 // keeps it marked dirty (in the modified state)
207 if (blk->isDirty()) {
208 pkt->setCacheResponding();
209 }
210 // on ReadExReq we give up our copy unconditionally,
211 // even if this cache is mostly inclusive, we may want
212 // to revisit this
213 invalidateBlock(blk);
214 } else if (blk->isWritable() && !pending_downgrade &&
215 !pkt->hasSharers() &&
216 pkt->cmd != MemCmd::ReadCleanReq) {
217 // we can give the requester a writable copy on a read
218 // request if:
219 // - we have a writable copy at this level (& below)
220 // - we don't have a pending snoop from below
221 // signaling another read request
222 // - no other cache above has a copy (otherwise it
223 // would have set hasSharers flag when
224 // snooping the packet)
225 // - the read has explicitly asked for a clean
226 // copy of the line
227 if (blk->isDirty()) {
228 // special considerations if we're owner:
229 if (!deferred_response) {
230 // respond with the line in Modified state
231 // (cacheResponding set, hasSharers not set)
232 pkt->setCacheResponding();
233
234 if (clusivity == Enums::mostly_excl) {
235 // if this cache is mostly exclusive with
236 // respect to the cache above, drop the
237 // block, no need to first unset the dirty
238 // bit
239 invalidateBlock(blk);
240 } else {
241 // if this cache is mostly inclusive, we
242 // keep the block in the Exclusive state,
243 // and pass it upwards as Modified
244 // (writable and dirty), hence we have
245 // multiple caches, all on the same path
246 // towards memory, all considering the
247 // same block writable, but only one
248 // considering it Modified
249
250 // we get away with multiple caches (on
251 // the same path to memory) considering
252 // the block writeable as we always enter
253 // the cache hierarchy through a cache,
254 // and first snoop upwards in all other
255 // branches
256 blk->status &= ~BlkDirty;
257 }
258 } else {
259 // if we're responding after our own miss,
260 // there's a window where the recipient didn't
261 // know it was getting ownership and may not
262 // have responded to snoops correctly, so we
263 // have to respond with a shared line
264 pkt->setHasSharers();
265 }
266 }
267 } else {
268 // otherwise only respond with a shared copy
269 pkt->setHasSharers();
270 }
271 }
272 } else {
273 // Upgrade or Invalidate
274 assert(pkt->isUpgrade() || pkt->isInvalidate());
275
276 // for invalidations we could be looking at the temp block
277 // (for upgrades we always allocate)
278 invalidateBlock(blk);
279 DPRINTF(Cache, "%s for %s addr %#llx size %d (invalidation)\n",
280 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
281 }
282}
283
284
285/////////////////////////////////////////////////////
286//
287// MSHR helper functions
288//
289/////////////////////////////////////////////////////
290
291
292void
293Cache::markInService(MSHR *mshr, bool pending_modified_resp)
294{
295 markInServiceInternal(mshr, pending_modified_resp);
296}
297
298/////////////////////////////////////////////////////
299//
300// Access path: requests coming in from the CPU side
301//
302/////////////////////////////////////////////////////
303
304bool
305Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
306 PacketList &writebacks)
307{
308 // sanity check
309 assert(pkt->isRequest());
310
311 chatty_assert(!(isReadOnly && pkt->isWrite()),
312 "Should never see a write in a read-only cache %s\n",
313 name());
314
315 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
316 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
317
318 if (pkt->req->isUncacheable()) {
319 DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(),
320 pkt->req->isInstFetch() ? " (ifetch)" : "",
321 pkt->getAddr());
322
323 // flush and invalidate any existing block
324 CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure()));
325 if (old_blk && old_blk->isValid()) {
326 if (old_blk->isDirty() || writebackClean)
327 writebacks.push_back(writebackBlk(old_blk));
328 else
329 writebacks.push_back(cleanEvictBlk(old_blk));
330 tags->invalidate(old_blk);
331 old_blk->invalidate();
332 }
333
334 blk = NULL;
335 // lookupLatency is the latency in case the request is uncacheable.
336 lat = lookupLatency;
337 return false;
338 }
339
340 ContextID id = pkt->req->hasContextId() ?
341 pkt->req->contextId() : InvalidContextID;
342 // Here lat is the value passed as parameter to accessBlock() function
343 // that can modify its value.
344 blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id);
345
346 DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(),
347 pkt->req->isInstFetch() ? " (ifetch)" : "",
348 pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns",
349 blk ? "hit " + blk->print() : "miss");
350
351
352 if (pkt->isEviction()) {
353 // We check for presence of block in above caches before issuing
354 // Writeback or CleanEvict to write buffer. Therefore the only
355 // possible cases can be of a CleanEvict packet coming from above
356 // encountering a Writeback generated in this cache peer cache and
357 // waiting in the write buffer. Cases of upper level peer caches
358 // generating CleanEvict and Writeback or simply CleanEvict and
359 // CleanEvict almost simultaneously will be caught by snoops sent out
360 // by crossbar.
361 std::vector<MSHR *> outgoing;
362 if (writeBuffer.findMatches(pkt->getAddr(), pkt->isSecure(),
363 outgoing)) {
364 assert(outgoing.size() == 1);
365 MSHR *wb_entry = outgoing[0];
366 assert(wb_entry->getNumTargets() == 1);
367 PacketPtr wbPkt = wb_entry->getTarget()->pkt;
368 assert(wbPkt->isWriteback());
369
370 if (pkt->isCleanEviction()) {
371 // The CleanEvict and WritebackClean snoops into other
372 // peer caches of the same level while traversing the
373 // crossbar. If a copy of the block is found, the
374 // packet is deleted in the crossbar. Hence, none of
375 // the other upper level caches connected to this
376 // cache have the block, so we can clear the
377 // BLOCK_CACHED flag in the Writeback if set and
378 // discard the CleanEvict by returning true.
379 wbPkt->clearBlockCached();
380 return true;
381 } else {
382 assert(pkt->cmd == MemCmd::WritebackDirty);
383 // Dirty writeback from above trumps our clean
384 // writeback... discard here
385 // Note: markInService will remove entry from writeback buffer.
386 markInService(wb_entry, false);
387 delete wbPkt;
388 }
389 }
390 }
391
392 // Writeback handling is special case. We can write the block into
393 // the cache without having a writeable copy (or any copy at all).
394 if (pkt->isWriteback()) {
395 assert(blkSize == pkt->getSize());
396
397 // we could get a clean writeback while we are having
398 // outstanding accesses to a block, do the simple thing for
399 // now and drop the clean writeback so that we do not upset
400 // any ordering/decisions about ownership already taken
401 if (pkt->cmd == MemCmd::WritebackClean &&
402 mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
403 DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
404 "dropping\n", pkt->getAddr());
405 return true;
406 }
407
408 if (blk == NULL) {
409 // need to do a replacement
410 blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
411 if (blk == NULL) {
412 // no replaceable block available: give up, fwd to next level.
413 incMissCount(pkt);
414 return false;
415 }
416 tags->insertBlock(pkt, blk);
417
418 blk->status = (BlkValid | BlkReadable);
419 if (pkt->isSecure()) {
420 blk->status |= BlkSecure;
421 }
422 }
423 // only mark the block dirty if we got a writeback command,
424 // and leave it as is for a clean writeback
425 if (pkt->cmd == MemCmd::WritebackDirty) {
426 blk->status |= BlkDirty;
427 }
428 // if the packet does not have sharers, it is passing
429 // writable, and we got the writeback in Modified or Exclusive
430 // state, if not we are in the Owned or Shared state
431 if (!pkt->hasSharers()) {
432 blk->status |= BlkWritable;
433 }
434 // nothing else to do; writeback doesn't expect response
435 assert(!pkt->needsResponse());
436 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize);
437 DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
438 incHitCount(pkt);
439 return true;
440 } else if (pkt->cmd == MemCmd::CleanEvict) {
441 if (blk != NULL) {
442 // Found the block in the tags, need to stop CleanEvict from
443 // propagating further down the hierarchy. Returning true will
444 // treat the CleanEvict like a satisfied write request and delete
445 // it.
446 return true;
447 }
448 // We didn't find the block here, propagate the CleanEvict further
449 // down the memory hierarchy. Returning false will treat the CleanEvict
450 // like a Writeback which could not find a replaceable block so has to
451 // go to next level.
452 return false;
453 } else if ((blk != NULL) &&
454 (pkt->needsWritable() ? blk->isWritable() : blk->isReadable())) {
455 // OK to satisfy access
456 incHitCount(pkt);
457 satisfyCpuSideRequest(pkt, blk);
458 return true;
459 }
460
461 // Can't satisfy access normally... either no block (blk == NULL)
462 // or have block but need writable
463
464 incMissCount(pkt);
465
466 if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) {
467 // complete miss on store conditional... just give up now
468 pkt->req->setExtraData(0);
469 return true;
470 }
471
472 return false;
473}
474
475void
476Cache::doWritebacks(PacketList& writebacks, Tick forward_time)
477{
478 while (!writebacks.empty()) {
479 PacketPtr wbPkt = writebacks.front();
480 // We use forwardLatency here because we are copying writebacks to
481 // write buffer. Call isCachedAbove for both Writebacks and
482 // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag
483 // in Writebacks and discard CleanEvicts.
484 if (isCachedAbove(wbPkt)) {
485 if (wbPkt->cmd == MemCmd::CleanEvict) {
486 // Delete CleanEvict because cached copies exist above. The
487 // packet destructor will delete the request object because
488 // this is a non-snoop request packet which does not require a
489 // response.
490 delete wbPkt;
491 } else if (wbPkt->cmd == MemCmd::WritebackClean) {
492 // clean writeback, do not send since the block is
493 // still cached above
494 assert(writebackClean);
495 delete wbPkt;
496 } else {
497 assert(wbPkt->cmd == MemCmd::WritebackDirty);
498 // Set BLOCK_CACHED flag in Writeback and send below, so that
499 // the Writeback does not reset the bit corresponding to this
500 // address in the snoop filter below.
501 wbPkt->setBlockCached();
502 allocateWriteBuffer(wbPkt, forward_time);
503 }
504 } else {
505 // If the block is not cached above, send packet below. Both
506 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
507 // reset the bit corresponding to this address in the snoop filter
508 // below.
509 allocateWriteBuffer(wbPkt, forward_time);
510 }
511 writebacks.pop_front();
512 }
513}
514
515void
516Cache::doWritebacksAtomic(PacketList& writebacks)
517{
518 while (!writebacks.empty()) {
519 PacketPtr wbPkt = writebacks.front();
520 // Call isCachedAbove for both Writebacks and CleanEvicts. If
521 // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks
522 // and discard CleanEvicts.
523 if (isCachedAbove(wbPkt, false)) {
524 if (wbPkt->cmd == MemCmd::WritebackDirty) {
525 // Set BLOCK_CACHED flag in Writeback and send below,
526 // so that the Writeback does not reset the bit
527 // corresponding to this address in the snoop filter
528 // below. We can discard CleanEvicts because cached
529 // copies exist above. Atomic mode isCachedAbove
530 // modifies packet to set BLOCK_CACHED flag
531 memSidePort->sendAtomic(wbPkt);
532 }
533 } else {
534 // If the block is not cached above, send packet below. Both
535 // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
536 // reset the bit corresponding to this address in the snoop filter
537 // below.
538 memSidePort->sendAtomic(wbPkt);
539 }
540 writebacks.pop_front();
541 // In case of CleanEvicts, the packet destructor will delete the
542 // request object because this is a non-snoop request packet which
543 // does not require a response.
544 delete wbPkt;
545 }
546}
547
548
549void
550Cache::recvTimingSnoopResp(PacketPtr pkt)
551{
552 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
553 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
554
555 assert(pkt->isResponse());
556 assert(!system->bypassCaches());
557
558 // determine if the response is from a snoop request we created
559 // (in which case it should be in the outstandingSnoop), or if we
560 // merely forwarded someone else's snoop request
561 const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) ==
562 outstandingSnoop.end();
563
564 if (!forwardAsSnoop) {
565 // the packet came from this cache, so sink it here and do not
566 // forward it
567 assert(pkt->cmd == MemCmd::HardPFResp);
568
569 outstandingSnoop.erase(pkt->req);
570
571 DPRINTF(Cache, "Got prefetch response from above for addr "
572 "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
573 recvTimingResp(pkt);
574 return;
575 }
576
577 // forwardLatency is set here because there is a response from an
578 // upper level cache.
579 // To pay the delay that occurs if the packet comes from the bus,
580 // we charge also headerDelay.
581 Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay;
582 // Reset the timing of the packet.
583 pkt->headerDelay = pkt->payloadDelay = 0;
584 memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time);
585}
586
587void
588Cache::promoteWholeLineWrites(PacketPtr pkt)
589{
590 // Cache line clearing instructions
591 if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
592 (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
593 pkt->cmd = MemCmd::WriteLineReq;
594 DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
595 }
596}
597
598bool
599Cache::recvTimingReq(PacketPtr pkt)
600{
601 DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print());
602
603 assert(pkt->isRequest());
604
605 // Just forward the packet if caches are disabled.
606 if (system->bypassCaches()) {
607 // @todo This should really enqueue the packet rather
608 bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
609 assert(success);
610 return true;
611 }
612
613 promoteWholeLineWrites(pkt);
614
615 if (pkt->cacheResponding()) {
616 // a cache above us (but not where the packet came from) is
617 // responding to the request, in other words it has the line
618 // in Modified or Owned state
619 DPRINTF(Cache, "Cache above responding to %#llx (%s): "
620 "not responding\n",
621 pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
622
623 // if the packet needs the block to be writable, and the cache
624 // that has promised to respond (setting the cache responding
625 // flag) is not providing writable (it is in Owned rather than
626 // the Modified state), we know that there may be other Shared
627 // copies in the system; go out and invalidate them all
628 if (pkt->needsWritable() && !pkt->responderHadWritable()) {
629 // an upstream cache that had the line in Owned state
630 // (dirty, but not writable), is responding and thus
631 // transferring the dirty line from one branch of the
632 // cache hierarchy to another
633
634 // send out an express snoop and invalidate all other
635 // copies (snooping a packet that needs writable is the
636 // same as an invalidation), thus turning the Owned line
637 // into a Modified line, note that we don't invalidate the
638 // block in the current cache or any other cache on the
639 // path to memory
640
641 // create a downstream express snoop with cleared packet
642 // flags, there is no need to allocate any data as the
643 // packet is merely used to co-ordinate state transitions
644 Packet *snoop_pkt = new Packet(pkt, true, false);
645
646 // also reset the bus time that the original packet has
647 // not yet paid for
648 snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0;
649
650 // make this an instantaneous express snoop, and let the
651 // other caches in the system know that the another cache
652 // is responding, because we have found the authorative
653 // copy (Modified or Owned) that will supply the right
654 // data
655 snoop_pkt->setExpressSnoop();
656 snoop_pkt->setCacheResponding();
657
658 // this express snoop travels towards the memory, and at
659 // every crossbar it is snooped upwards thus reaching
660 // every cache in the system
661 bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt);
662 // express snoops always succeed
663 assert(success);
664
665 // main memory will delete the snoop packet
666 }
667
668 // queue for deletion, as opposed to immediate deletion, as
669 // the sending cache is still relying on the packet
670 pendingDelete.reset(pkt);
671
672 // no need to take any action in this particular cache as an
673 // upstream cache has already committed to responding, and
674 // either the packet does not need writable (and we can let
675 // the cache that set the cache responding flag pass on the
676 // line without any need for intervention), or if the packet
677 // needs writable it is provided, or we have already sent out
678 // any express snoops in the section above
679 return true;
680 }
681
682 // anything that is merely forwarded pays for the forward latency and
683 // the delay provided by the crossbar
684 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
685
686 // We use lookupLatency here because it is used to specify the latency
687 // to access.
688 Cycles lat = lookupLatency;
689 CacheBlk *blk = NULL;
690 bool satisfied = false;
691 {
692 PacketList writebacks;
693 // Note that lat is passed by reference here. The function
694 // access() calls accessBlock() which can modify lat value.
695 satisfied = access(pkt, blk, lat, writebacks);
696
697 // copy writebacks to write buffer here to ensure they logically
698 // proceed anything happening below
699 doWritebacks(writebacks, forward_time);
700 }
701
702 // Here we charge the headerDelay that takes into account the latencies
703 // of the bus, if the packet comes from it.
704 // The latency charged it is just lat that is the value of lookupLatency
705 // modified by access() function, or if not just lookupLatency.
706 // In case of a hit we are neglecting response latency.
707 // In case of a miss we are neglecting forward latency.
708 Tick request_time = clockEdge(lat) + pkt->headerDelay;
709 // Here we reset the timing of the packet.
710 pkt->headerDelay = pkt->payloadDelay = 0;
711
712 // track time of availability of next prefetch, if any
713 Tick next_pf_time = MaxTick;
714
715 bool needsResponse = pkt->needsResponse();
716
717 if (satisfied) {
718 // should never be satisfying an uncacheable access as we
719 // flush and invalidate any existing block as part of the
720 // lookup
721 assert(!pkt->req->isUncacheable());
722
723 // hit (for all other request types)
724
725 if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) {
726 if (blk)
727 blk->status &= ~BlkHWPrefetched;
728
729 // Don't notify on SWPrefetch
730 if (!pkt->cmd.isSWPrefetch())
731 next_pf_time = prefetcher->notify(pkt);
732 }
733
734 if (needsResponse) {
735 pkt->makeTimingResponse();
736 // @todo: Make someone pay for this
737 pkt->headerDelay = pkt->payloadDelay = 0;
738
739 // In this case we are considering request_time that takes
740 // into account the delay of the xbar, if any, and just
741 // lat, neglecting responseLatency, modelling hit latency
742 // just as lookupLatency or or the value of lat overriden
743 // by access(), that calls accessBlock() function.
744 cpuSidePort->schedTimingResp(pkt, request_time, true);
745 } else {
746 DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n",
747 __func__, pkt->cmdString(), pkt->getAddr(),
748 pkt->getSize());
749
750 // queue the packet for deletion, as the sending cache is
751 // still relying on it; if the block is found in access(),
752 // CleanEvict and Writeback messages will be deleted
753 // here as well
754 pendingDelete.reset(pkt);
755 }
756 } else {
757 // miss
758
759 Addr blk_addr = blockAlign(pkt->getAddr());
760
761 // ignore any existing MSHR if we are dealing with an
762 // uncacheable request
763 MSHR *mshr = pkt->req->isUncacheable() ? nullptr :
764 mshrQueue.findMatch(blk_addr, pkt->isSecure());
765
766 // Software prefetch handling:
767 // To keep the core from waiting on data it won't look at
768 // anyway, send back a response with dummy data. Miss handling
769 // will continue asynchronously. Unfortunately, the core will
770 // insist upon freeing original Packet/Request, so we have to
771 // create a new pair with a different lifecycle. Note that this
772 // processing happens before any MSHR munging on the behalf of
773 // this request because this new Request will be the one stored
774 // into the MSHRs, not the original.
775 if (pkt->cmd.isSWPrefetch()) {
776 assert(needsResponse);
777 assert(pkt->req->hasPaddr());
778 assert(!pkt->req->isUncacheable());
779
780 // There's no reason to add a prefetch as an additional target
781 // to an existing MSHR. If an outstanding request is already
782 // in progress, there is nothing for the prefetch to do.
783 // If this is the case, we don't even create a request at all.
784 PacketPtr pf = nullptr;
785
786 if (!mshr) {
787 // copy the request and create a new SoftPFReq packet
788 RequestPtr req = new Request(pkt->req->getPaddr(),
789 pkt->req->getSize(),
790 pkt->req->getFlags(),
791 pkt->req->masterId());
792 pf = new Packet(req, pkt->cmd);
793 pf->allocate();
794 assert(pf->getAddr() == pkt->getAddr());
795 assert(pf->getSize() == pkt->getSize());
796 }
797
798 pkt->makeTimingResponse();
799 // for debugging, set all the bits in the response data
800 // (also keeps valgrind from complaining when debugging settings
801 // print out instruction results)
802 std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize());
803 // request_time is used here, taking into account lat and the delay
804 // charged if the packet comes from the xbar.
805 cpuSidePort->schedTimingResp(pkt, request_time, true);
806
807 // If an outstanding request is in progress (we found an
808 // MSHR) this is set to null
809 pkt = pf;
810 }
811
812 if (mshr) {
813 /// MSHR hit
814 /// @note writebacks will be checked in getNextMSHR()
815 /// for any conflicting requests to the same block
816
817 //@todo remove hw_pf here
818
819 // Coalesce unless it was a software prefetch (see above).
820 if (pkt) {
821 assert(!pkt->isWriteback());
822 // CleanEvicts corresponding to blocks which have
823 // outstanding requests in MSHRs are simply sunk here
824 if (pkt->cmd == MemCmd::CleanEvict) {
825 pendingDelete.reset(pkt);
826 } else {
827 DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n",
828 __func__, pkt->cmdString(), pkt->getAddr(),
829 pkt->getSize());
830
831 assert(pkt->req->masterId() < system->maxMasters());
832 mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
833 // We use forward_time here because it is the same
834 // considering new targets. We have multiple
835 // requests for the same address here. It
836 // specifies the latency to allocate an internal
837 // buffer and to schedule an event to the queued
838 // port and also takes into account the additional
839 // delay of the xbar.
840 mshr->allocateTarget(pkt, forward_time, order++,
841 allocOnFill(pkt->cmd));
842 if (mshr->getNumTargets() == numTarget) {
843 noTargetMSHR = mshr;
844 setBlocked(Blocked_NoTargets);
845 // need to be careful with this... if this mshr isn't
846 // ready yet (i.e. time > curTick()), we don't want to
847 // move it ahead of mshrs that are ready
848 // mshrQueue.moveToFront(mshr);
849 }
850 }
851 // We should call the prefetcher reguardless if the request is
852 // satisfied or not, reguardless if the request is in the MSHR or
853 // not. The request could be a ReadReq hit, but still not
854 // satisfied (potentially because of a prior write to the same
855 // cache line. So, even when not satisfied, tehre is an MSHR
856 // already allocated for this, we need to let the prefetcher know
857 // about the request
858 if (prefetcher) {
859 // Don't notify on SWPrefetch
860 if (!pkt->cmd.isSWPrefetch())
861 next_pf_time = prefetcher->notify(pkt);
862 }
863 }
864 } else {
865 // no MSHR
866 assert(pkt->req->masterId() < system->maxMasters());
867 if (pkt->req->isUncacheable()) {
868 mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
869 } else {
870 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
871 }
872
873 if (pkt->isEviction() ||
874 (pkt->req->isUncacheable() && pkt->isWrite())) {
875 // We use forward_time here because there is an
876 // uncached memory write, forwarded to WriteBuffer.
877 allocateWriteBuffer(pkt, forward_time);
878 } else {
879 if (blk && blk->isValid()) {
880 // should have flushed and have no valid block
881 assert(!pkt->req->isUncacheable());
882
883 // If we have a write miss to a valid block, we
884 // need to mark the block non-readable. Otherwise
885 // if we allow reads while there's an outstanding
886 // write miss, the read could return stale data
887 // out of the cache block... a more aggressive
888 // system could detect the overlap (if any) and
889 // forward data out of the MSHRs, but we don't do
890 // that yet. Note that we do need to leave the
891 // block valid so that it stays in the cache, in
892 // case we get an upgrade response (and hence no
893 // new data) when the write miss completes.
894 // As long as CPUs do proper store/load forwarding
895 // internally, and have a sufficiently weak memory
896 // model, this is probably unnecessary, but at some
897 // point it must have seemed like we needed it...
898 assert(pkt->needsWritable());
899 assert(!blk->isWritable());
900 blk->status &= ~BlkReadable;
901 }
902 // Here we are using forward_time, modelling the latency of
903 // a miss (outbound) just as forwardLatency, neglecting the
904 // lookupLatency component.
905 allocateMissBuffer(pkt, forward_time);
906 }
907
908 if (prefetcher) {
909 // Don't notify on SWPrefetch
910 if (!pkt->cmd.isSWPrefetch())
911 next_pf_time = prefetcher->notify(pkt);
912 }
913 }
914 }
915
916 if (next_pf_time != MaxTick)
917 schedMemSideSendEvent(next_pf_time);
918
919 return true;
920}
921
922
923// See comment in cache.hh.
924PacketPtr
925Cache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
926 bool needsWritable) const
927{
928 bool blkValid = blk && blk->isValid();
929
930 if (cpu_pkt->req->isUncacheable()) {
931 // note that at the point we see the uncacheable request we
932 // flush any block, but there could be an outstanding MSHR,
933 // and the cache could have filled again before we actually
934 // send out the forwarded uncacheable request (blk could thus
935 // be non-null)
936 return NULL;
937 }
938
939 if (!blkValid &&
940 (cpu_pkt->isUpgrade() ||
941 cpu_pkt->isEviction())) {
942 // Writebacks that weren't allocated in access() and upgrades
943 // from upper-level caches that missed completely just go
944 // through.
945 return NULL;
946 }
947
948 assert(cpu_pkt->needsResponse());
949
950 MemCmd cmd;
951 // @TODO make useUpgrades a parameter.
952 // Note that ownership protocols require upgrade, otherwise a
953 // write miss on a shared owned block will generate a ReadExcl,
954 // which will clobber the owned copy.
955 const bool useUpgrades = true;
956 if (blkValid && useUpgrades) {
957 // only reason to be here is that blk is read only and we need
958 // it to be writable
959 assert(needsWritable);
960 assert(!blk->isWritable());
961 cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
962 } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
963 cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
964 // Even though this SC will fail, we still need to send out the
965 // request and get the data to supply it to other snoopers in the case
966 // where the determination the StoreCond fails is delayed due to
967 // all caches not being on the same local bus.
968 cmd = MemCmd::SCUpgradeFailReq;
969 } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
970 // forward as invalidate to all other caches, this gives us
971 // the line in Exclusive state, and invalidates all other
972 // copies
973 cmd = MemCmd::InvalidateReq;
974 } else {
975 // block is invalid
976 cmd = needsWritable ? MemCmd::ReadExReq :
977 (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
978 }
979 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
980
981 // if there are upstream caches that have already marked the
982 // packet as having sharers (not passing writable), pass that info
983 // downstream
984 if (cpu_pkt->hasSharers()) {
985 // note that cpu_pkt may have spent a considerable time in the
986 // MSHR queue and that the information could possibly be out
987 // of date, however, there is no harm in conservatively
988 // assuming the block has sharers
989 pkt->setHasSharers();
990 DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx "
991 "size %d\n",
992 __func__, cpu_pkt->cmdString(), pkt->cmdString(),
993 pkt->getAddr(), pkt->getSize());
994 }
995
996 // the packet should be block aligned
997 assert(pkt->getAddr() == blockAlign(pkt->getAddr()));
998
999 pkt->allocate();
1000 DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n",
1001 __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(),
1002 pkt->getSize());
1003 return pkt;
1004}
1005
1006
1007Tick
1008Cache::recvAtomic(PacketPtr pkt)
1009{
1010 // We are in atomic mode so we pay just for lookupLatency here.
1011 Cycles lat = lookupLatency;
1012 // @TODO: make this a parameter
1013 bool last_level_cache = false;
1014
1015 // Forward the request if the system is in cache bypass mode.
1016 if (system->bypassCaches())
1017 return ticksToCycles(memSidePort->sendAtomic(pkt));
1018
1019 promoteWholeLineWrites(pkt);
1020
1021 if (pkt->cacheResponding()) {
1022 // have to invalidate ourselves and any lower caches even if
1023 // upper cache will be responding
1024 if (pkt->isInvalidate()) {
1025 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1026 if (blk && blk->isValid()) {
1027 tags->invalidate(blk);
1028 blk->invalidate();
1029 DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):"
1030 " invalidating\n",
1031 pkt->cmdString(), pkt->getAddr(),
1032 pkt->isSecure() ? "s" : "ns");
1033 }
1034 if (!last_level_cache) {
1035 DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):"
1036 " forwarding\n",
1037 pkt->cmdString(), pkt->getAddr(),
1038 pkt->isSecure() ? "s" : "ns");
1039 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1040 }
1041 } else {
1042 DPRINTF(Cache, "Other cache responding to %s on %#llx: "
1043 "not responding\n",
1044 pkt->cmdString(), pkt->getAddr());
1045 }
1046
1047 return lat * clockPeriod();
1048 }
1049
1050 // should assert here that there are no outstanding MSHRs or
1051 // writebacks... that would mean that someone used an atomic
1052 // access in timing mode
1053
1054 CacheBlk *blk = NULL;
1055 PacketList writebacks;
1056 bool satisfied = access(pkt, blk, lat, writebacks);
1057
1058 // handle writebacks resulting from the access here to ensure they
1059 // logically proceed anything happening below
1060 doWritebacksAtomic(writebacks);
1061
1062 if (!satisfied) {
1063 // MISS
1064
1065 PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsWritable());
1066
1067 bool is_forward = (bus_pkt == NULL);
1068
1069 if (is_forward) {
1070 // just forwarding the same request to the next level
1071 // no local cache operation involved
1072 bus_pkt = pkt;
1073 }
1074
1075 DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n",
1076 bus_pkt->cmdString(), bus_pkt->getAddr(),
1077 bus_pkt->isSecure() ? "s" : "ns");
1078
1079#if TRACING_ON
1080 CacheBlk::State old_state = blk ? blk->status : 0;
1081#endif
1082
1083 lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
1084
1085 // We are now dealing with the response handling
1086 DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n",
1087 bus_pkt->cmdString(), bus_pkt->getAddr(),
1088 bus_pkt->isSecure() ? "s" : "ns",
1089 old_state);
1090
1091 // If packet was a forward, the response (if any) is already
1092 // in place in the bus_pkt == pkt structure, so we don't need
1093 // to do anything. Otherwise, use the separate bus_pkt to
1094 // generate response to pkt and then delete it.
1095 if (!is_forward) {
1096 if (pkt->needsResponse()) {
1097 assert(bus_pkt->isResponse());
1098 if (bus_pkt->isError()) {
1099 pkt->makeAtomicResponse();
1100 pkt->copyError(bus_pkt);
1101 } else if (pkt->cmd == MemCmd::InvalidateReq) {
1102 if (blk) {
1103 // invalidate response to a cache that received
1104 // an invalidate request
1105 satisfyCpuSideRequest(pkt, blk);
1106 }
1107 } else if (pkt->cmd == MemCmd::WriteLineReq) {
1108 // note the use of pkt, not bus_pkt here.
1109
1110 // write-line request to the cache that promoted
1111 // the write to a whole line
1112 blk = handleFill(pkt, blk, writebacks,
1113 allocOnFill(pkt->cmd));
1114 satisfyCpuSideRequest(pkt, blk);
1115 } else if (bus_pkt->isRead() ||
1116 bus_pkt->cmd == MemCmd::UpgradeResp) {
1117 // we're updating cache state to allow us to
1118 // satisfy the upstream request from the cache
1119 blk = handleFill(bus_pkt, blk, writebacks,
1120 allocOnFill(pkt->cmd));
1121 satisfyCpuSideRequest(pkt, blk);
1122 } else {
1123 // we're satisfying the upstream request without
1124 // modifying cache state, e.g., a write-through
1125 pkt->makeAtomicResponse();
1126 }
1127 }
1128 delete bus_pkt;
1129 }
1130 }
1131
1132 // Note that we don't invoke the prefetcher at all in atomic mode.
1133 // It's not clear how to do it properly, particularly for
1134 // prefetchers that aggressively generate prefetch candidates and
1135 // rely on bandwidth contention to throttle them; these will tend
1136 // to pollute the cache in atomic mode since there is no bandwidth
1137 // contention. If we ever do want to enable prefetching in atomic
1138 // mode, though, this is the place to do it... see timingAccess()
1139 // for an example (though we'd want to issue the prefetch(es)
1140 // immediately rather than calling requestMemSideBus() as we do
1141 // there).
1142
1143 // do any writebacks resulting from the response handling
1144 doWritebacksAtomic(writebacks);
1145
1146 // if we used temp block, check to see if its valid and if so
1147 // clear it out, but only do so after the call to recvAtomic is
1148 // finished so that any downstream observers (such as a snoop
1149 // filter), first see the fill, and only then see the eviction
1150 if (blk == tempBlock && tempBlock->isValid()) {
1151 // the atomic CPU calls recvAtomic for fetch and load/store
1152 // sequentuially, and we may already have a tempBlock
1153 // writeback from the fetch that we have not yet sent
1154 if (tempBlockWriteback) {
1155 // if that is the case, write the prevoius one back, and
1156 // do not schedule any new event
1157 writebackTempBlockAtomic();
1158 } else {
1159 // the writeback/clean eviction happens after the call to
1160 // recvAtomic has finished (but before any successive
1161 // calls), so that the response handling from the fill is
1162 // allowed to happen first
1163 schedule(writebackTempBlockAtomicEvent, curTick());
1164 }
1165
1166 tempBlockWriteback = (blk->isDirty() || writebackClean) ?
1167 writebackBlk(blk) : cleanEvictBlk(blk);
1168 blk->invalidate();
1169 }
1170
1171 if (pkt->needsResponse()) {
1172 pkt->makeAtomicResponse();
1173 }
1174
1175 return lat * clockPeriod();
1176}
1177
1178
1179void
1180Cache::functionalAccess(PacketPtr pkt, bool fromCpuSide)
1181{
1182 if (system->bypassCaches()) {
1183 // Packets from the memory side are snoop request and
1184 // shouldn't happen in bypass mode.
1185 assert(fromCpuSide);
1186
1187 // The cache should be flushed if we are in cache bypass mode,
1188 // so we don't need to check if we need to update anything.
1189 memSidePort->sendFunctional(pkt);
1190 return;
1191 }
1192
1193 Addr blk_addr = blockAlign(pkt->getAddr());
1194 bool is_secure = pkt->isSecure();
1195 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
1196 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
1197
1198 pkt->pushLabel(name());
1199
1200 CacheBlkPrintWrapper cbpw(blk);
1201
1202 // Note that just because an L2/L3 has valid data doesn't mean an
1203 // L1 doesn't have a more up-to-date modified copy that still
1204 // needs to be found. As a result we always update the request if
1205 // we have it, but only declare it satisfied if we are the owner.
1206
1207 // see if we have data at all (owned or otherwise)
1208 bool have_data = blk && blk->isValid()
1209 && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
1210 blk->data);
1211
1212 // data we have is dirty if marked as such or if we have an
1213 // in-service MSHR that is pending a modified line
1214 bool have_dirty =
1215 have_data && (blk->isDirty() ||
1216 (mshr && mshr->inService && mshr->isPendingModified()));
1217
1218 bool done = have_dirty
1219 || cpuSidePort->checkFunctional(pkt)
1220 || mshrQueue.checkFunctional(pkt, blk_addr)
1221 || writeBuffer.checkFunctional(pkt, blk_addr)
1222 || memSidePort->checkFunctional(pkt);
1223
1224 DPRINTF(Cache, "functional %s %#llx (%s) %s%s%s\n",
1225 pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns",
1226 (blk && blk->isValid()) ? "valid " : "",
1227 have_data ? "data " : "", done ? "done " : "");
1228
1229 // We're leaving the cache, so pop cache->name() label
1230 pkt->popLabel();
1231
1232 if (done) {
1233 pkt->makeResponse();
1234 } else {
1235 // if it came as a request from the CPU side then make sure it
1236 // continues towards the memory side
1237 if (fromCpuSide) {
1238 memSidePort->sendFunctional(pkt);
1239 } else if (forwardSnoops && cpuSidePort->isSnooping()) {
1240 // if it came from the memory side, it must be a snoop request
1241 // and we should only forward it if we are forwarding snoops
1242 cpuSidePort->sendFunctionalSnoop(pkt);
1243 }
1244 }
1245}
1246
1247
1248/////////////////////////////////////////////////////
1249//
1250// Response handling: responses from the memory side
1251//
1252/////////////////////////////////////////////////////
1253
1254
1255void
1256Cache::recvTimingResp(PacketPtr pkt)
1257{
1258 assert(pkt->isResponse());
1259
1260 // all header delay should be paid for by the crossbar, unless
1261 // this is a prefetch response from above
1262 panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
1263 "%s saw a non-zero packet delay\n", name());
1264
1265 MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
1266 bool is_error = pkt->isError();
1267
1268 assert(mshr);
1269
1270 if (is_error) {
1271 DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), "
1272 "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns",
1273 pkt->cmdString());
1274 }
1275
1276 DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n",
1277 pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1278 pkt->isSecure() ? "s" : "ns");
1279
1280 MSHRQueue *mq = mshr->queue;
1281 bool wasFull = mq->isFull();
1282
1283 if (mshr == noTargetMSHR) {
1284 // we always clear at least one target
1285 clearBlocked(Blocked_NoTargets);
1286 noTargetMSHR = NULL;
1287 }
1288
1289 // Initial target is used just for stats
1290 MSHR::Target *initial_tgt = mshr->getTarget();
1291 int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
1292 Tick miss_latency = curTick() - initial_tgt->recvTime;
1293 PacketList writebacks;
1294 // We need forward_time here because we have a call of
1295 // allocateWriteBuffer() that need this parameter to specify the
1296 // time to request the bus. In this case we use forward latency
1297 // because there is a writeback. We pay also here for headerDelay
1298 // that is charged of bus latencies if the packet comes from the
1299 // bus.
1300 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1301
1302 if (pkt->req->isUncacheable()) {
1303 assert(pkt->req->masterId() < system->maxMasters());
1304 mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
1305 miss_latency;
1306 } else {
1307 assert(pkt->req->masterId() < system->maxMasters());
1308 mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
1309 miss_latency;
1310 }
1311
1312 // upgrade deferred targets if the response has no sharers, and is
1313 // thus passing writable
1314 if (!pkt->hasSharers()) {
1315 mshr->promoteWritable();
1316 }
1317
1318 bool is_fill = !mshr->isForward &&
1319 (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
1320
1321 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
1322
1323 if (is_fill && !is_error) {
1324 DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
1325 pkt->getAddr());
1326
1327 blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill);
1328 assert(blk != NULL);
1329 }
1330
1331 // allow invalidation responses originating from write-line
1332 // requests to be discarded
1333 bool is_invalidate = pkt->isInvalidate();
1334
1335 // First offset for critical word first calculations
1336 int initial_offset = initial_tgt->pkt->getOffset(blkSize);
1337
1338 while (mshr->hasTargets()) {
1339 MSHR::Target *target = mshr->getTarget();
1340 Packet *tgt_pkt = target->pkt;
1341
1342 switch (target->source) {
1343 case MSHR::Target::FromCPU:
1344 Tick completion_time;
1345 // Here we charge on completion_time the delay of the xbar if the
1346 // packet comes from it, charged on headerDelay.
1347 completion_time = pkt->headerDelay;
1348
1349 // Software prefetch handling for cache closest to core
1350 if (tgt_pkt->cmd.isSWPrefetch()) {
1351 // a software prefetch would have already been ack'd immediately
1352 // with dummy data so the core would be able to retire it.
1353 // this request completes right here, so we deallocate it.
1354 delete tgt_pkt->req;
1355 delete tgt_pkt;
1356 break; // skip response
1357 }
1358
1359 // unlike the other packet flows, where data is found in other
1360 // caches or memory and brought back, write-line requests always
1361 // have the data right away, so the above check for "is fill?"
1362 // cannot actually be determined until examining the stored MSHR
1363 // state. We "catch up" with that logic here, which is duplicated
1364 // from above.
1365 if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
1366 assert(!is_error);
1367 // we got the block in a writable state, so promote
1368 // any deferred targets if possible
1369 mshr->promoteWritable();
1370 // NB: we use the original packet here and not the response!
1371 blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill);
1372 assert(blk != NULL);
1373
1374 // treat as a fill, and discard the invalidation
1375 // response
1376 is_fill = true;
1377 is_invalidate = false;
1378 }
1379
1380 if (is_fill) {
1381 satisfyCpuSideRequest(tgt_pkt, blk,
1382 true, mshr->hasPostDowngrade());
1383
1384 // How many bytes past the first request is this one
1385 int transfer_offset =
1386 tgt_pkt->getOffset(blkSize) - initial_offset;
1387 if (transfer_offset < 0) {
1388 transfer_offset += blkSize;
1389 }
1390
1391 // If not critical word (offset) return payloadDelay.
1392 // responseLatency is the latency of the return path
1393 // from lower level caches/memory to an upper level cache or
1394 // the core.
1395 completion_time += clockEdge(responseLatency) +
1396 (transfer_offset ? pkt->payloadDelay : 0);
1397
1398 assert(!tgt_pkt->req->isUncacheable());
1399
1400 assert(tgt_pkt->req->masterId() < system->maxMasters());
1401 missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
1402 completion_time - target->recvTime;
1403 } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
1404 // failed StoreCond upgrade
1405 assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
1406 tgt_pkt->cmd == MemCmd::StoreCondFailReq ||
1407 tgt_pkt->cmd == MemCmd::SCUpgradeFailReq);
1408 // responseLatency is the latency of the return path
1409 // from lower level caches/memory to an upper level cache or
1410 // the core.
1411 completion_time += clockEdge(responseLatency) +
1412 pkt->payloadDelay;
1413 tgt_pkt->req->setExtraData(0);
1414 } else {
1415 // not a cache fill, just forwarding response
1416 // responseLatency is the latency of the return path
1417 // from lower level cahces/memory to the core.
1418 completion_time += clockEdge(responseLatency) +
1419 pkt->payloadDelay;
1420 if (pkt->isRead() && !is_error) {
1421 // sanity check
1422 assert(pkt->getAddr() == tgt_pkt->getAddr());
1423 assert(pkt->getSize() >= tgt_pkt->getSize());
1424
1425 tgt_pkt->setData(pkt->getConstPtr<uint8_t>());
1426 }
1427 }
1428 tgt_pkt->makeTimingResponse();
1429 // if this packet is an error copy that to the new packet
1430 if (is_error)
1431 tgt_pkt->copyError(pkt);
1432 if (tgt_pkt->cmd == MemCmd::ReadResp &&
1433 (is_invalidate || mshr->hasPostInvalidate())) {
1434 // If intermediate cache got ReadRespWithInvalidate,
1435 // propagate that. Response should not have
1436 // isInvalidate() set otherwise.
1437 tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate;
1438 DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n",
1439 __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr());
1440 }
1441 // Reset the bus additional time as it is now accounted for
1442 tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
1443 cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
1444 break;
1445
1446 case MSHR::Target::FromPrefetcher:
1447 assert(tgt_pkt->cmd == MemCmd::HardPFReq);
1448 if (blk)
1449 blk->status |= BlkHWPrefetched;
1450 delete tgt_pkt->req;
1451 delete tgt_pkt;
1452 break;
1453
1454 case MSHR::Target::FromSnoop:
1455 // I don't believe that a snoop can be in an error state
1456 assert(!is_error);
1457 // response to snoop request
1458 DPRINTF(Cache, "processing deferred snoop...\n");
1459 assert(!(is_invalidate && !mshr->hasPostInvalidate()));
1460 handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
1461 break;
1462
1463 default:
1464 panic("Illegal target->source enum %d\n", target->source);
1465 }
1466
1467 mshr->popTarget();
1468 }
1469
1470 if (blk && blk->isValid()) {
1471 // an invalidate response stemming from a write line request
1472 // should not invalidate the block, so check if the
1473 // invalidation should be discarded
1474 if (is_invalidate || mshr->hasPostInvalidate()) {
1475 invalidateBlock(blk);
1476 } else if (mshr->hasPostDowngrade()) {
1477 blk->status &= ~BlkWritable;
1478 }
1479 }
1480
1481 if (mshr->promoteDeferredTargets()) {
1482 // avoid later read getting stale data while write miss is
1483 // outstanding.. see comment in timingAccess()
1484 if (blk) {
1485 blk->status &= ~BlkReadable;
1486 }
1487 mq = mshr->queue;
1488 mq->markPending(mshr);
1489 schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
1490 } else {
1491 mq->deallocate(mshr);
1492 if (wasFull && !mq->isFull()) {
1493 clearBlocked((BlockedCause)mq->index);
1494 }
1495
1496 // Request the bus for a prefetch if this deallocation freed enough
1497 // MSHRs for a prefetch to take place
1498 if (prefetcher && mq == &mshrQueue && mshrQueue.canPrefetch()) {
1499 Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
1500 clockEdge());
1501 if (next_pf_time != MaxTick)
1502 schedMemSideSendEvent(next_pf_time);
1503 }
1504 }
1505 // reset the xbar additional timinig as it is now accounted for
1506 pkt->headerDelay = pkt->payloadDelay = 0;
1507
1508 // copy writebacks to write buffer
1509 doWritebacks(writebacks, forward_time);
1510
1511 // if we used temp block, check to see if its valid and then clear it out
1512 if (blk == tempBlock && tempBlock->isValid()) {
1513 // We use forwardLatency here because we are copying
1514 // Writebacks/CleanEvicts to write buffer. It specifies the latency to
1515 // allocate an internal buffer and to schedule an event to the
1516 // queued port.
1517 if (blk->isDirty() || writebackClean) {
1518 PacketPtr wbPkt = writebackBlk(blk);
1519 allocateWriteBuffer(wbPkt, forward_time);
1520 // Set BLOCK_CACHED flag if cached above.
1521 if (isCachedAbove(wbPkt))
1522 wbPkt->setBlockCached();
1523 } else {
1524 PacketPtr wcPkt = cleanEvictBlk(blk);
1525 // Check to see if block is cached above. If not allocate
1526 // write buffer
1527 if (isCachedAbove(wcPkt))
1528 delete wcPkt;
1529 else
1530 allocateWriteBuffer(wcPkt, forward_time);
1531 }
1532 blk->invalidate();
1533 }
1534
1535 DPRINTF(Cache, "Leaving %s with %s for addr %#llx\n", __func__,
1536 pkt->cmdString(), pkt->getAddr());
1537 delete pkt;
1538}
1539
1540PacketPtr
1541Cache::writebackBlk(CacheBlk *blk)
1542{
1543 chatty_assert(!isReadOnly || writebackClean,
1544 "Writeback from read-only cache");
1545 assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
1546
1547 writebacks[Request::wbMasterId]++;
1548
1549 Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set),
1550 blkSize, 0, Request::wbMasterId);
1551 if (blk->isSecure())
1552 req->setFlags(Request::SECURE);
1553
1554 req->taskId(blk->task_id);
1555 blk->task_id= ContextSwitchTaskId::Unknown;
1556 blk->tickInserted = curTick();
1557
1558 PacketPtr pkt =
1559 new Packet(req, blk->isDirty() ?
1560 MemCmd::WritebackDirty : MemCmd::WritebackClean);
1561
1562 DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n",
1563 pkt->getAddr(), blk->isWritable(), blk->isDirty());
1564
1565 if (blk->isWritable()) {
1566 // not asserting shared means we pass the block in modified
1567 // state, mark our own block non-writeable
1568 blk->status &= ~BlkWritable;
1569 } else {
1570 // we are in the Owned state, tell the receiver
1571 pkt->setHasSharers();
1572 }
1573
1574 // make sure the block is not marked dirty
1575 blk->status &= ~BlkDirty;
1576
1577 pkt->allocate();
1578 std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize);
1579
1580 return pkt;
1581}
1582
1583PacketPtr
1584Cache::cleanEvictBlk(CacheBlk *blk)
1585{
1586 assert(!writebackClean);
1587 assert(blk && blk->isValid() && !blk->isDirty());
1588 // Creating a zero sized write, a message to the snoop filter
1589 Request *req =
1590 new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
1591 Request::wbMasterId);
1592 if (blk->isSecure())
1593 req->setFlags(Request::SECURE);
1594
1595 req->taskId(blk->task_id);
1596 blk->task_id = ContextSwitchTaskId::Unknown;
1597 blk->tickInserted = curTick();
1598
1599 PacketPtr pkt = new Packet(req, MemCmd::CleanEvict);
1600 pkt->allocate();
1601 DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(),
1602 pkt->req->isInstFetch() ? " (ifetch)" : "",
1603 pkt->getAddr());
1604
1605 return pkt;
1606}
1607
1608void
1609Cache::memWriteback()
1610{
1611 CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor);
1612 tags->forEachBlk(visitor);
1613}
1614
1615void
1616Cache::memInvalidate()
1617{
1618 CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor);
1619 tags->forEachBlk(visitor);
1620}
1621
1622bool
1623Cache::isDirty() const
1624{
1625 CacheBlkIsDirtyVisitor visitor;
1626 tags->forEachBlk(visitor);
1627
1628 return visitor.isDirty();
1629}
1630
1631bool
1632Cache::writebackVisitor(CacheBlk &blk)
1633{
1634 if (blk.isDirty()) {
1635 assert(blk.isValid());
1636
1637 Request request(tags->regenerateBlkAddr(blk.tag, blk.set),
1638 blkSize, 0, Request::funcMasterId);
1639 request.taskId(blk.task_id);
1640
1641 Packet packet(&request, MemCmd::WriteReq);
1642 packet.dataStatic(blk.data);
1643
1644 memSidePort->sendFunctional(&packet);
1645
1646 blk.status &= ~BlkDirty;
1647 }
1648
1649 return true;
1650}
1651
1652bool
1653Cache::invalidateVisitor(CacheBlk &blk)
1654{
1655
1656 if (blk.isDirty())
1657 warn_once("Invalidating dirty cache lines. Expect things to break.\n");
1658
1659 if (blk.isValid()) {
1660 assert(!blk.isDirty());
1661 tags->invalidate(&blk);
1662 blk.invalidate();
1663 }
1664
1665 return true;
1666}
1667
1668CacheBlk*
1669Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1670{
1671 CacheBlk *blk = tags->findVictim(addr);
1672
1673 // It is valid to return NULL if there is no victim
1674 if (!blk)
1675 return nullptr;
1676
1677 if (blk->isValid()) {
1678 Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set);
1679 MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
1680 if (repl_mshr) {
1681 // must be an outstanding upgrade request
1682 // on a block we're about to replace...
1683 assert(!blk->isWritable() || blk->isDirty());
1684 assert(repl_mshr->needsWritable());
1685 // too hard to replace block with transient state
1686 // allocation failed, block not inserted
1687 return NULL;
1688 } else {
1689 DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n",
1690 repl_addr, blk->isSecure() ? "s" : "ns",
1691 addr, is_secure ? "s" : "ns",
1692 blk->isDirty() ? "writeback" : "clean");
1693
1694 // Will send up Writeback/CleanEvict snoops via isCachedAbove
1695 // when pushing this writeback list into the write buffer.
1696 if (blk->isDirty() || writebackClean) {
1697 // Save writeback packet for handling by caller
1698 writebacks.push_back(writebackBlk(blk));
1699 } else {
1700 writebacks.push_back(cleanEvictBlk(blk));
1701 }
1702 }
1703 }
1704
1705 return blk;
1706}
1707
1708void
1709Cache::invalidateBlock(CacheBlk *blk)
1710{
1711 if (blk != tempBlock)
1712 tags->invalidate(blk);
1713 blk->invalidate();
1714}
1715
1716// Note that the reason we return a list of writebacks rather than
1717// inserting them directly in the write buffer is that this function
1718// is called by both atomic and timing-mode accesses, and in atomic
1719// mode we don't mess with the write buffer (we just perform the
1720// writebacks atomically once the original request is complete).
1721CacheBlk*
1722Cache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
1723 bool allocate)
1724{
1725 assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
1726 Addr addr = pkt->getAddr();
1727 bool is_secure = pkt->isSecure();
1728#if TRACING_ON
1729 CacheBlk::State old_state = blk ? blk->status : 0;
1730#endif
1731
1732 // When handling a fill, discard any CleanEvicts for the
1733 // same address in write buffer.
1734 Addr M5_VAR_USED blk_addr = blockAlign(pkt->getAddr());
1735 std::vector<MSHR *> M5_VAR_USED wbs;
1736 assert (!writeBuffer.findMatches(blk_addr, is_secure, wbs));
1737
1738 if (blk == NULL) {
1739 // better have read new data...
1740 assert(pkt->hasData());
1741
1742 // only read responses and write-line requests have data;
1743 // note that we don't write the data here for write-line - that
1744 // happens in the subsequent satisfyCpuSideRequest.
1745 assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
1746
1747 // need to do a replacement if allocating, otherwise we stick
1748 // with the temporary storage
1749 blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL;
1750
1751 if (blk == NULL) {
1752 // No replaceable block or a mostly exclusive
1753 // cache... just use temporary storage to complete the
1754 // current request and then get rid of it
1755 assert(!tempBlock->isValid());
1756 blk = tempBlock;
1757 tempBlock->set = tags->extractSet(addr);
1758 tempBlock->tag = tags->extractTag(addr);
1759 // @todo: set security state as well...
1760 DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
1761 is_secure ? "s" : "ns");
1762 } else {
1763 tags->insertBlock(pkt, blk);
1764 }
1765
1766 // we should never be overwriting a valid block
1767 assert(!blk->isValid());
1768 } else {
1769 // existing block... probably an upgrade
1770 assert(blk->tag == tags->extractTag(addr));
1771 // either we're getting new data or the block should already be valid
1772 assert(pkt->hasData() || blk->isValid());
1773 // don't clear block status... if block is already dirty we
1774 // don't want to lose that
1775 }
1776
1777 if (is_secure)
1778 blk->status |= BlkSecure;
1779 blk->status |= BlkValid | BlkReadable;
1780
1781 // sanity check for whole-line writes, which should always be
1782 // marked as writable as part of the fill, and then later marked
1783 // dirty as part of satisfyCpuSideRequest
1784 if (pkt->cmd == MemCmd::WriteLineReq) {
1785 assert(!pkt->hasSharers());
1786 // at the moment other caches do not respond to the
1787 // invalidation requests corresponding to a whole-line write
1788 assert(!pkt->cacheResponding());
1789 }
1790
1791 // here we deal with setting the appropriate state of the line,
1792 // and we start by looking at the hasSharers flag, and ignore the
1793 // cacheResponding flag (normally signalling dirty data) if the
1794 // packet has sharers, thus the line is never allocated as Owned
1795 // (dirty but not writable), and always ends up being either
1796 // Shared, Exclusive or Modified, see Packet::setCacheResponding
1797 // for more details
1798 if (!pkt->hasSharers()) {
1799 // we could get a writable line from memory (rather than a
1800 // cache) even in a read-only cache, note that we set this bit
1801 // even for a read-only cache, possibly revisit this decision
1802 blk->status |= BlkWritable;
1803
1804 // check if we got this via cache-to-cache transfer (i.e., from a
1805 // cache that had the block in Modified or Owned state)
1806 if (pkt->cacheResponding()) {
1807 // we got the block in Modified state, and invalidated the
1808 // owners copy
1809 blk->status |= BlkDirty;
1810
1811 chatty_assert(!isReadOnly, "Should never see dirty snoop response "
1812 "in read-only cache %s\n", name());
1813 }
1814 }
1815
1816 DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
1817 addr, is_secure ? "s" : "ns", old_state, blk->print());
1818
1819 // if we got new data, copy it in (checking for a read response
1820 // and a response that has data is the same in the end)
1821 if (pkt->isRead()) {
1822 // sanity checks
1823 assert(pkt->hasData());
1824 assert(pkt->getSize() == blkSize);
1825
1826 std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize);
1827 }
1828 // We pay for fillLatency here.
1829 blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
1830 pkt->payloadDelay;
1831
1832 return blk;
1833}
1834
1835
1836/////////////////////////////////////////////////////
1837//
1838// Snoop path: requests coming in from the memory side
1839//
1840/////////////////////////////////////////////////////
1841
1842void
1843Cache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
1844 bool already_copied, bool pending_inval)
1845{
1846 // sanity check
1847 assert(req_pkt->isRequest());
1848 assert(req_pkt->needsResponse());
1849
1850 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
1851 req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize());
1852 // timing-mode snoop responses require a new packet, unless we
1853 // already made a copy...
1854 PacketPtr pkt = req_pkt;
1855 if (!already_copied)
1856 // do not clear flags, and allocate space for data if the
1857 // packet needs it (the only packets that carry data are read
1858 // responses)
1859 pkt = new Packet(req_pkt, false, req_pkt->isRead());
1860
1861 assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() ||
1862 pkt->hasSharers());
1863 pkt->makeTimingResponse();
1864 if (pkt->isRead()) {
1865 pkt->setDataFromBlock(blk_data, blkSize);
1866 }
1867 if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
1868 // Assume we defer a response to a read from a far-away cache
1869 // A, then later defer a ReadExcl from a cache B on the same
1870 // bus as us. We'll assert cacheResponding in both cases, but
1871 // in the latter case cacheResponding will keep the
1872 // invalidation from reaching cache A. This special response
1873 // tells cache A that it gets the block to satisfy its read,
1874 // but must immediately invalidate it.
1875 pkt->cmd = MemCmd::ReadRespWithInvalidate;
1876 }
1877 // Here we consider forward_time, paying for just forward latency and
1878 // also charging the delay provided by the xbar.
1879 // forward_time is used as send_time in next allocateWriteBuffer().
1880 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1881 // Here we reset the timing of the packet.
1882 pkt->headerDelay = pkt->payloadDelay = 0;
1883 DPRINTF(Cache, "%s created response: %s addr %#llx size %d tick: %lu\n",
1884 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1885 forward_time);
1886 memSidePort->schedTimingSnoopResp(pkt, forward_time, true);
1887}
1888
1889uint32_t
1890Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
1891 bool is_deferred, bool pending_inval)
1892{
1893 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
1894 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1895 // deferred snoops can only happen in timing mode
1896 assert(!(is_deferred && !is_timing));
1897 // pending_inval only makes sense on deferred snoops
1898 assert(!(pending_inval && !is_deferred));
1899 assert(pkt->isRequest());
1900
1901 // the packet may get modified if we or a forwarded snooper
1902 // responds in atomic mode, so remember a few things about the
1903 // original packet up front
1904 bool invalidate = pkt->isInvalidate();
1905 bool M5_VAR_USED needs_writable = pkt->needsWritable();
1906
1907 // at the moment we could get an uncacheable write which does not
1908 // have the invalidate flag, and we need a suitable way of dealing
1909 // with this case
1910 panic_if(invalidate && pkt->req->isUncacheable(),
1911 "%s got an invalidating uncacheable snoop request %s to %#llx",
1912 name(), pkt->cmdString(), pkt->getAddr());
1913
1914 uint32_t snoop_delay = 0;
1915
1916 if (forwardSnoops) {
1917 // first propagate snoop upward to see if anyone above us wants to
1918 // handle it. save & restore packet src since it will get
1919 // rewritten to be relative to cpu-side bus (if any)
1920 bool alreadyResponded = pkt->cacheResponding();
1921 if (is_timing) {
1922 // copy the packet so that we can clear any flags before
1923 // forwarding it upwards, we also allocate data (passing
1924 // the pointer along in case of static data), in case
1925 // there is a snoop hit in upper levels
1926 Packet snoopPkt(pkt, true, true);
1927 snoopPkt.setExpressSnoop();
1928 // the snoop packet does not need to wait any additional
1929 // time
1930 snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
1931 cpuSidePort->sendTimingSnoopReq(&snoopPkt);
1932
1933 // add the header delay (including crossbar and snoop
1934 // delays) of the upward snoop to the snoop delay for this
1935 // cache
1936 snoop_delay += snoopPkt.headerDelay;
1937
1938 if (snoopPkt.cacheResponding()) {
1939 // cache-to-cache response from some upper cache
1940 assert(!alreadyResponded);
1941 pkt->setCacheResponding();
1942 }
1943 // upstream cache has the block, or has an outstanding
1944 // MSHR, pass the flag on
1945 if (snoopPkt.hasSharers()) {
1946 pkt->setHasSharers();
1947 }
1948 // If this request is a prefetch or clean evict and an upper level
1949 // signals block present, make sure to propagate the block
1950 // presence to the requester.
1951 if (snoopPkt.isBlockCached()) {
1952 pkt->setBlockCached();
1953 }
1954 } else {
1955 cpuSidePort->sendAtomicSnoop(pkt);
1956 if (!alreadyResponded && pkt->cacheResponding()) {
1957 // cache-to-cache response from some upper cache:
1958 // forward response to original requester
1959 assert(pkt->isResponse());
1960 }
1961 }
1962 }
1963
1964 if (!blk || !blk->isValid()) {
1965 DPRINTF(Cache, "%s snoop miss for %s addr %#llx size %d\n",
1966 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1967 return snoop_delay;
1968 } else {
1969 DPRINTF(Cache, "%s snoop hit for %s for addr %#llx size %d, "
1970 "old state is %s\n", __func__, pkt->cmdString(),
1971 pkt->getAddr(), pkt->getSize(), blk->print());
1972 }
1973
1974 chatty_assert(!(isReadOnly && blk->isDirty()),
1975 "Should never have a dirty block in a read-only cache %s\n",
1976 name());
1977
1978 // We may end up modifying both the block state and the packet (if
1979 // we respond in atomic mode), so just figure out what to do now
1980 // and then do it later. If we find dirty data while snooping for
1981 // an invalidate, we don't need to send a response. The
1982 // invalidation itself is taken care of below.
1983 bool respond = blk->isDirty() && pkt->needsResponse() &&
1984 pkt->cmd != MemCmd::InvalidateReq;
1985 bool have_writable = blk->isWritable();
1986
1987 // Invalidate any prefetch's from below that would strip write permissions
1988 // MemCmd::HardPFReq is only observed by upstream caches. After missing
1989 // above and in it's own cache, a new MemCmd::ReadReq is created that
1990 // downstream caches observe.
1991 if (pkt->mustCheckAbove()) {
1992 DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from"
1993 " lower cache\n", pkt->getAddr(), pkt->cmdString());
1994 pkt->setBlockCached();
1995 return snoop_delay;
1996 }
1997
1998 if (pkt->isRead() && !invalidate) {
1999 // reading without requiring the line in a writable state
2000 assert(!needs_writable);
2001 pkt->setHasSharers();
2002
2003 // if the requesting packet is uncacheable, retain the line in
2004 // the current state, otherwhise unset the writable flag,
2005 // which means we go from Modified to Owned (and will respond
2006 // below), remain in Owned (and will respond below), from
2007 // Exclusive to Shared, or remain in Shared
2008 if (!pkt->req->isUncacheable())
2009 blk->status &= ~BlkWritable;
2010 }
2011
2012 if (respond) {
2013 // prevent anyone else from responding, cache as well as
2014 // memory, and also prevent any memory from even seeing the
2015 // request
2016 pkt->setCacheResponding();
2017 if (have_writable) {
2018 // inform the cache hierarchy that this cache had the line
2019 // in the Modified state so that we avoid unnecessary
2020 // invalidations (see Packet::setResponderHadWritable)
2021 pkt->setResponderHadWritable();
2022
2023 // in the case of an uncacheable request there is no point
2024 // in setting the responderHadWritable flag, but since the
2025 // recipient does not care there is no harm in doing so
2026 } else {
2027 // if the packet has needsWritable set we invalidate our
2028 // copy below and all other copies will be invalidates
2029 // through express snoops, and if needsWritable is not set
2030 // we already called setHasSharers above
2031 }
2032
2033 // if we are returning a writable and dirty (Modified) line,
2034 // we should be invalidating the line
2035 panic_if(!invalidate && !pkt->hasSharers(),
2036 "%s is passing a Modified line through %s to %#llx, "
2037 "but keeping the block",
2038 name(), pkt->cmdString(), pkt->getAddr());
2039
2040 if (is_timing) {
2041 doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
2042 } else {
2043 pkt->makeAtomicResponse();
2044 pkt->setDataFromBlock(blk->data, blkSize);
2045 }
2046 }
2047
2048 if (!respond && is_timing && is_deferred) {
2049 // if it's a deferred timing snoop to which we are not
2050 // responding, then we've made a copy of both the request and
2051 // the packet, delete them here
2052 assert(pkt->needsResponse());
2053 delete pkt->req;
2054 delete pkt;
2055 }
2056
2057 // Do this last in case it deallocates block data or something
2058 // like that
2059 if (invalidate) {
2060 invalidateBlock(blk);
2061 }
2062
2063 DPRINTF(Cache, "new state is %s\n", blk->print());
2064
2065 return snoop_delay;
2066}
2067
2068
2069void
2070Cache::recvTimingSnoopReq(PacketPtr pkt)
2071{
2072 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
2073 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
2074
2075 // Snoops shouldn't happen when bypassing caches
2076 assert(!system->bypassCaches());
2077
2078 // no need to snoop requests that are not in range
2079 if (!inRange(pkt->getAddr())) {
2080 return;
2081 }
2082
2083 bool is_secure = pkt->isSecure();
2084 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
2085
2086 Addr blk_addr = blockAlign(pkt->getAddr());
2087 MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
2088
2089 // Update the latency cost of the snoop so that the crossbar can
2090 // account for it. Do not overwrite what other neighbouring caches
2091 // have already done, rather take the maximum. The update is
2092 // tentative, for cases where we return before an upward snoop
2093 // happens below.
2094 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay,
2095 lookupLatency * clockPeriod());
2096
2097 // Inform request(Prefetch, CleanEvict or Writeback) from below of
2098 // MSHR hit, set setBlockCached.
2099 if (mshr && pkt->mustCheckAbove()) {
2100 DPRINTF(Cache, "Setting block cached for %s from"
2101 "lower cache on mshr hit %#x\n",
2102 pkt->cmdString(), pkt->getAddr());
2103 pkt->setBlockCached();
2104 return;
2105 }
2106
2107 // Let the MSHR itself track the snoop and decide whether we want
2108 // to go ahead and do the regular cache snoop
2109 if (mshr && mshr->handleSnoop(pkt, order++)) {
2110 DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)."
2111 "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns",
2112 mshr->print());
2113
2114 if (mshr->getNumTargets() > numTarget)
2115 warn("allocating bonus target for snoop"); //handle later
2116 return;
2117 }
2118
2119 //We also need to check the writeback buffers and handle those
2120 std::vector<MSHR *> writebacks;
2121 if (writeBuffer.findMatches(blk_addr, is_secure, writebacks)) {
2122 DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n",
2123 pkt->getAddr(), is_secure ? "s" : "ns");
2124
2125 // Look through writebacks for any cachable writes.
2126 // We should only ever find a single match
2127 assert(writebacks.size() == 1);
2128 MSHR *wb_entry = writebacks[0];
2129 // Expect to see only Writebacks and/or CleanEvicts here, both of
2130 // which should not be generated for uncacheable data.
2131 assert(!wb_entry->isUncacheable());
2132 // There should only be a single request responsible for generating
2133 // Writebacks/CleanEvicts.
2134 assert(wb_entry->getNumTargets() == 1);
2135 PacketPtr wb_pkt = wb_entry->getTarget()->pkt;
2136 assert(wb_pkt->isEviction());
2137
2138 if (pkt->isEviction()) {
2139 // if the block is found in the write queue, set the BLOCK_CACHED
2140 // flag for Writeback/CleanEvict snoop. On return the snoop will
2141 // propagate the BLOCK_CACHED flag in Writeback packets and prevent
2142 // any CleanEvicts from travelling down the memory hierarchy.
2143 pkt->setBlockCached();
2144 DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit"
2145 " %#x\n", pkt->cmdString(), pkt->getAddr());
2146 return;
2147 }
2148
2149 if (wb_pkt->cmd == MemCmd::WritebackDirty) {
2150 // we have dirty data, and so will proceed to respond
2151 pkt->setCacheResponding();
2152 if (!pkt->needsWritable()) {
2153 // the packet should end up in the Shared state (non
2154 // writable) on the completion of the fill
2155 pkt->setHasSharers();
2156 // similarly, the writeback is no longer passing
2157 // writeable (the receiving cache should consider the
2158 // block Owned rather than Modified)
2159 wb_pkt->setHasSharers();
2160 } else {
2161 // we need to invalidate our copy. we do that
2162 // below.
2163 assert(pkt->isInvalidate());
2164 }
2165 doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(),
2166 false, false);
2167 } else {
2168 // on hitting a clean writeback we play it safe and do not
2169 // provide a response, the block may be dirty somewhere
2170 // else
2171 assert(wb_pkt->isCleanEviction());
2172 // The cache technically holds the block until the
2173 // corresponding message reaches the crossbar
2174 // below. Therefore when a snoop encounters a CleanEvict
2175 // or WritebackClean message we must call
2176 // setHasSharers (just like when it encounters a
2177 // Writeback) to avoid the snoop filter prematurely
2178 // clearing the holder bit in the crossbar below
2179 if (!pkt->needsWritable()) {
2180 pkt->setHasSharers();
2181 // the writeback is no longer passing writeable (the
2182 // receiving cache should consider the block Owned
2183 // rather than Modified)
2184 wb_pkt->setHasSharers();
2185 } else {
2186 assert(pkt->isInvalidate());
2187 }
2188 }
2189
2190 if (pkt->isInvalidate()) {
2191 // Invalidation trumps our writeback... discard here
2192 // Note: markInService will remove entry from writeback buffer.
2193 markInService(wb_entry, false);
2194 delete wb_pkt;
2195 }
2196 }
2197
2198 // If this was a shared writeback, there may still be
2199 // other shared copies above that require invalidation.
2200 // We could be more selective and return here if the
2201 // request is non-exclusive or if the writeback is
2202 // exclusive.
2203 uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false);
2204
2205 // Override what we did when we first saw the snoop, as we now
2206 // also have the cost of the upwards snoops to account for
2207 pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay +
2208 lookupLatency * clockPeriod());
2209}
2210
2211bool
2212Cache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
2213{
2214 // Express snoop responses from master to slave, e.g., from L1 to L2
2215 cache->recvTimingSnoopResp(pkt);
2216 return true;
2217}
2218
2219Tick
2220Cache::recvAtomicSnoop(PacketPtr pkt)
2221{
2222 // Snoops shouldn't happen when bypassing caches
2223 assert(!system->bypassCaches());
2224
2225 // no need to snoop requests that are not in range.
2226 if (!inRange(pkt->getAddr())) {
2227 return 0;
2228 }
2229
2230 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
2231 uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false);
2232 return snoop_delay + lookupLatency * clockPeriod();
2233}
2234
2235
2236MSHR *
2237Cache::getNextMSHR()
2238{
2239 // Check both MSHR queue and write buffer for potential requests,
2240 // note that null does not mean there is no request, it could
2241 // simply be that it is not ready
2242 MSHR *miss_mshr = mshrQueue.getNextMSHR();
2243 MSHR *write_mshr = writeBuffer.getNextMSHR();
2244
2245 // If we got a write buffer request ready, first priority is a
2246 // full write buffer, otherwhise we favour the miss requests
2247 if (write_mshr &&
2248 ((writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) ||
2249 !miss_mshr)) {
2250 // need to search MSHR queue for conflicting earlier miss.
2251 MSHR *conflict_mshr =
2252 mshrQueue.findPending(write_mshr->blkAddr,
2253 write_mshr->isSecure);
2254
2255 if (conflict_mshr && conflict_mshr->order < write_mshr->order) {
2256 // Service misses in order until conflict is cleared.
2257 return conflict_mshr;
2258
2259 // @todo Note that we ignore the ready time of the conflict here
2260 }
2261
2262 // No conflicts; issue write
2263 return write_mshr;
2264 } else if (miss_mshr) {
2265 // need to check for conflicting earlier writeback
2266 MSHR *conflict_mshr =
2267 writeBuffer.findPending(miss_mshr->blkAddr,
2268 miss_mshr->isSecure);
2269 if (conflict_mshr) {
2270 // not sure why we don't check order here... it was in the
2271 // original code but commented out.
2272
2273 // The only way this happens is if we are
2274 // doing a write and we didn't have permissions
2275 // then subsequently saw a writeback (owned got evicted)
2276 // We need to make sure to perform the writeback first
2277 // To preserve the dirty data, then we can issue the write
2278
2279 // should we return write_mshr here instead? I.e. do we
2280 // have to flush writes in order? I don't think so... not
2281 // for Alpha anyway. Maybe for x86?
2282 return conflict_mshr;
2283
2284 // @todo Note that we ignore the ready time of the conflict here
2285 }
2286
2287 // No conflicts; issue read
2288 return miss_mshr;
2289 }
2290
2291 // fall through... no pending requests. Try a prefetch.
2292 assert(!miss_mshr && !write_mshr);
2293 if (prefetcher && mshrQueue.canPrefetch()) {
2294 // If we have a miss queue slot, we can try a prefetch
2295 PacketPtr pkt = prefetcher->getPacket();
2296 if (pkt) {
2297 Addr pf_addr = blockAlign(pkt->getAddr());
2298 if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
2299 !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
2300 !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
2301 // Update statistic on number of prefetches issued
2302 // (hwpf_mshr_misses)
2303 assert(pkt->req->masterId() < system->maxMasters());
2304 mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
2305
2306 // allocate an MSHR and return it, note
2307 // that we send the packet straight away, so do not
2308 // schedule the send
2309 return allocateMissBuffer(pkt, curTick(), false);
2310 } else {
2311 // free the request and packet
2312 delete pkt->req;
2313 delete pkt;
2314 }
2315 }
2316 }
2317
2318 return NULL;
2319}
2320
2321bool
2322Cache::isCachedAbove(PacketPtr pkt, bool is_timing) const
2323{
2324 if (!forwardSnoops)
2325 return false;
2326 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
2327 // Writeback snoops into upper level caches to check for copies of the
2328 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
2329 // packet, the cache can inform the crossbar below of presence or absence
2330 // of the block.
2331 if (is_timing) {
2332 Packet snoop_pkt(pkt, true, false);
2333 snoop_pkt.setExpressSnoop();
2334 // Assert that packet is either Writeback or CleanEvict and not a
2335 // prefetch request because prefetch requests need an MSHR and may
2336 // generate a snoop response.
2337 assert(pkt->isEviction());
2338 snoop_pkt.senderState = NULL;
2339 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2340 // Writeback/CleanEvict snoops do not generate a snoop response.
2341 assert(!(snoop_pkt.cacheResponding()));
2342 return snoop_pkt.isBlockCached();
2343 } else {
2344 cpuSidePort->sendAtomicSnoop(pkt);
2345 return pkt->isBlockCached();
2346 }
2347}
2348
2349PacketPtr
2350Cache::getTimingPacket()
2351{
2352 MSHR *mshr = getNextMSHR();
2353
2354 if (mshr == NULL) {
2355 return NULL;
2356 }
2357
2358 // use request from 1st target
2359 PacketPtr tgt_pkt = mshr->getTarget()->pkt;
2360 PacketPtr pkt = NULL;
2361
2362 DPRINTF(CachePort, "%s %s for addr %#llx size %d\n", __func__,
2363 tgt_pkt->cmdString(), tgt_pkt->getAddr(), tgt_pkt->getSize());
2364
2365 CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
2366
2367 if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) {
2368 // We need to check the caches above us to verify that
2369 // they don't have a copy of this block in the dirty state
2370 // at the moment. Without this check we could get a stale
2371 // copy from memory that might get used in place of the
2372 // dirty one.
2373 Packet snoop_pkt(tgt_pkt, true, false);
2374 snoop_pkt.setExpressSnoop();
2375 // We are sending this packet upwards, but if it hits we will
2376 // get a snoop response that we end up treating just like a
2377 // normal response, hence it needs the MSHR as its sender
2378 // state
2379 snoop_pkt.senderState = mshr;
2380 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2381
2382 // Check to see if the prefetch was squashed by an upper cache (to
2383 // prevent us from grabbing the line) or if a Check to see if a
2384 // writeback arrived between the time the prefetch was placed in
2385 // the MSHRs and when it was selected to be sent or if the
2386 // prefetch was squashed by an upper cache.
2387
2388 // It is important to check cacheResponding before
2389 // prefetchSquashed. If another cache has committed to
2390 // responding, it will be sending a dirty response which will
2391 // arrive at the MSHR allocated for this request. Checking the
2392 // prefetchSquash first may result in the MSHR being
2393 // prematurely deallocated.
2394 if (snoop_pkt.cacheResponding()) {
2395 auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req);
2396 assert(r.second);
2397
2398 // if we are getting a snoop response with no sharers it
2399 // will be allocated as Modified
2400 bool pending_modified_resp = !snoop_pkt.hasSharers();
2401 markInService(mshr, pending_modified_resp);
2402
2403 DPRINTF(Cache, "Upward snoop of prefetch for addr"
2404 " %#x (%s) hit\n",
2405 tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns");
2406 return NULL;
2407 }
2408
2409 if (snoop_pkt.isBlockCached() || blk != NULL) {
2410 DPRINTF(Cache, "Block present, prefetch squashed by cache. "
2411 "Deallocating mshr target %#x.\n",
2412 mshr->blkAddr);
2413 // Deallocate the mshr target
2414 if (mshr->queue->forceDeallocateTarget(mshr)) {
2415 // Clear block if this deallocation resulted freed an
2416 // mshr when all had previously been utilized
2417 clearBlocked((BlockedCause)(mshr->queue->index));
2418 }
2419 return NULL;
2420 }
2421 }
2422
2423 if (mshr->isForwardNoResponse()) {
2424 // no response expected, just forward packet as it is
2425 assert(tags->findBlock(mshr->blkAddr, mshr->isSecure) == NULL);
2426 pkt = tgt_pkt;
2427 } else {
2428 pkt = getBusPacket(tgt_pkt, blk, mshr->needsWritable());
2429
2430 mshr->isForward = (pkt == NULL);
2431
2432 if (mshr->isForward) {
2433 // not a cache block request, but a response is expected
2434 // make copy of current packet to forward, keep current
2435 // copy for response handling
2436 pkt = new Packet(tgt_pkt, false, true);
2437 if (pkt->isWrite()) {
2438 pkt->setData(tgt_pkt->getConstPtr<uint8_t>());
2439 }
2440 }
2441 }
2442
2443 assert(pkt != NULL);
2444 // play it safe and append (rather than set) the sender state, as
2445 // forwarded packets may already have existing state
2446 pkt->pushSenderState(mshr);
2447 return pkt;
2448}
2449
2450
2451Tick
2452Cache::nextMSHRReadyTime() const
2453{
2454 Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(),
2455 writeBuffer.nextMSHRReadyTime());
2456
2457 // Don't signal prefetch ready time if no MSHRs available
2458 // Will signal once enoguh MSHRs are deallocated
2459 if (prefetcher && mshrQueue.canPrefetch()) {
2460 nextReady = std::min(nextReady,
2461 prefetcher->nextPrefetchReadyTime());
2462 }
2463
2464 return nextReady;
2465}
2466
2467void
2468Cache::serialize(CheckpointOut &cp) const
2469{
2470 bool dirty(isDirty());
2471
2472 if (dirty) {
2473 warn("*** The cache still contains dirty data. ***\n");
2474 warn(" Make sure to drain the system using the correct flags.\n");
2475 warn(" This checkpoint will not restore correctly and dirty data in "
2476 "the cache will be lost!\n");
2477 }
2478
2479 // Since we don't checkpoint the data in the cache, any dirty data
2480 // will be lost when restoring from a checkpoint of a system that
2481 // wasn't drained properly. Flag the checkpoint as invalid if the
2482 // cache contains dirty data.
2483 bool bad_checkpoint(dirty);
2484 SERIALIZE_SCALAR(bad_checkpoint);
2485}
2486
2487void
2488Cache::unserialize(CheckpointIn &cp)
2489{
2490 bool bad_checkpoint;
2491 UNSERIALIZE_SCALAR(bad_checkpoint);
2492 if (bad_checkpoint) {
2493 fatal("Restoring from checkpoints with dirty caches is not supported "
2494 "in the classic memory system. Please remove any caches or "
2495 " drain them properly before taking checkpoints.\n");
2496 }
2497}
2498
2499///////////////
2500//
2501// CpuSidePort
2502//
2503///////////////
2504
2505AddrRangeList
2506Cache::CpuSidePort::getAddrRanges() const
2507{
2508 return cache->getAddrRanges();
2509}
2510
2511bool
2512Cache::CpuSidePort::recvTimingReq(PacketPtr pkt)
2513{
2514 assert(!cache->system->bypassCaches());
2515
2516 bool success = false;
2517
2518 // always let packets through if an upstream cache has committed
2519 // to responding, even if blocked (we should technically look at
2520 // the isExpressSnoop flag, but it is set by the cache itself, and
2521 // consequently we have to rely on the cacheResponding flag)
2522 if (pkt->cacheResponding()) {
2523 // do not change the current retry state
2524 bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
2525 assert(bypass_success);
2526 return true;
2527 } else if (blocked || mustSendRetry) {
2528 // either already committed to send a retry, or blocked
2529 success = false;
2530 } else {
2531 // pass it on to the cache, and let the cache decide if we
2532 // have to retry or not
2533 success = cache->recvTimingReq(pkt);
2534 }
2535
2536 // remember if we have to retry
2537 mustSendRetry = !success;
2538 return success;
2539}
2540
2541Tick
2542Cache::CpuSidePort::recvAtomic(PacketPtr pkt)
2543{
2544 return cache->recvAtomic(pkt);
2545}
2546
2547void
2548Cache::CpuSidePort::recvFunctional(PacketPtr pkt)
2549{
2550 // functional request
2551 cache->functionalAccess(pkt, true);
2552}
2553
2554Cache::
2555CpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
2556 const std::string &_label)
2557 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
2558{
2559}
2560
2561Cache*
2562CacheParams::create()
2563{
2564 assert(tags);
2565
2566 return new Cache(this);
2567}
2568///////////////
2569//
2570// MemSidePort
2571//
2572///////////////
2573
2574bool
2575Cache::MemSidePort::recvTimingResp(PacketPtr pkt)
2576{
2577 cache->recvTimingResp(pkt);
2578 return true;
2579}
2580
2581// Express snooping requests to memside port
2582void
2583Cache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
2584{
2585 // handle snooping requests
2586 cache->recvTimingSnoopReq(pkt);
2587}
2588
2589Tick
2590Cache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
2591{
2592 return cache->recvAtomicSnoop(pkt);
2593}
2594
2595void
2596Cache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
2597{
2598 // functional snoop (note that in contrast to atomic we don't have
2599 // a specific functionalSnoop method, as they have the same
2600 // behaviour regardless)
2601 cache->functionalAccess(pkt, false);
2602}
2603
2604void
2605Cache::CacheReqPacketQueue::sendDeferredPacket()
2606{
2607 // sanity check
2608 assert(!waitingOnRetry);
2609
2610 // there should never be any deferred request packets in the
2611 // queue, instead we resly on the cache to provide the packets
2612 // from the MSHR queue or write queue
2613 assert(deferredPacketReadyTime() == MaxTick);
2614
2615 // check for request packets (requests & writebacks)
2616 PacketPtr pkt = cache.getTimingPacket();
2617 if (pkt == NULL) {
2618 // can happen if e.g. we attempt a writeback and fail, but
2619 // before the retry, the writeback is eliminated because
2620 // we snoop another cache's ReadEx.
2621 } else {
2622 MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
2623 // in most cases getTimingPacket allocates a new packet, and
2624 // we must delete it unless it is successfully sent
2625 bool delete_pkt = !mshr->isForwardNoResponse();
2626
2627 // let our snoop responses go first if there are responses to
2628 // the same addresses we are about to writeback, note that
2629 // this creates a dependency between requests and snoop
2630 // responses, but that should not be a problem since there is
2631 // a chain already and the key is that the snoop responses can
2632 // sink unconditionally
2633 if (snoopRespQueue.hasAddr(pkt->getAddr())) {
2634 DPRINTF(CachePort, "Waiting for snoop response to be sent\n");
2635 Tick when = snoopRespQueue.deferredPacketReadyTime();
2636 schedSendEvent(when);
2637
2638 if (delete_pkt)
2639 delete pkt;
2640
2641 return;
2642 }
2643
2644
2645 waitingOnRetry = !masterPort.sendTimingReq(pkt);
2646
2647 if (waitingOnRetry) {
2648 DPRINTF(CachePort, "now waiting on a retry\n");
2649 if (delete_pkt) {
2650 // we are awaiting a retry, but we
2651 // delete the packet and will be creating a new packet
2652 // when we get the opportunity
2653 delete pkt;
2654 }
2655 // note that we have now masked any requestBus and
2656 // schedSendEvent (we will wait for a retry before
2657 // doing anything), and this is so even if we do not
2658 // care about this packet and might override it before
2659 // it gets retried
2660 } else {
2661 // As part of the call to sendTimingReq the packet is
2662 // forwarded to all neighbouring caches (and any caches
2663 // above them) as a snoop. Thus at this point we know if
2664 // any of the neighbouring caches are responding, and if
2665 // so, we know it is dirty, and we can determine if it is
2666 // being passed as Modified, making our MSHR the ordering
2667 // point
2668 bool pending_modified_resp = !pkt->hasSharers() &&
2669 pkt->cacheResponding();
2670
2671 cache.markInService(mshr, pending_modified_resp);
2672 }
2673 }
2674
2675 // if we succeeded and are not waiting for a retry, schedule the
2676 // next send considering when the next MSHR is ready, note that
2677 // snoop responses have their own packet queue and thus schedule
2678 // their own events
2679 if (!waitingOnRetry) {
2680 schedSendEvent(cache.nextMSHRReadyTime());
2681 }
2682}
2683
2684Cache::
2685MemSidePort::MemSidePort(const std::string &_name, Cache *_cache,
2686 const std::string &_label)
2687 : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
2688 _reqQueue(*_cache, *this, _snoopRespQueue, _label),
2689 _snoopRespQueue(*_cache, *this, _label), cache(_cache)
2690{
2691}