1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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472 return;
473 }
474
475 BaseCache::recvTimingReq(pkt);
476}
477
478PacketPtr
479Cache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
480 bool needsWritable) const
481{
482 // should never see evictions here
483 assert(!cpu_pkt->isEviction());
484
485 bool blkValid = blk && blk->isValid();
486
487 if (cpu_pkt->req->isUncacheable() ||
488 (!blkValid && cpu_pkt->isUpgrade()) ||

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495 assert(cpu_pkt->needsResponse());
496
497 MemCmd cmd;
498 // @TODO make useUpgrades a parameter.
499 // Note that ownership protocols require upgrade, otherwise a
500 // write miss on a shared owned block will generate a ReadExcl,
501 // which will clobber the owned copy.
502 const bool useUpgrades = true;
503 if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
504 assert(!blkValid || !blk->isWritable());
505 // forward as invalidate to all other caches, this gives us
506 // the line in Exclusive state, and invalidates all other
507 // copies
508 cmd = MemCmd::InvalidateReq;
509 } else if (blkValid && useUpgrades) {
510 // only reason to be here is that blk is read only and we need
511 // it to be writable

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575 assert(!(pkt->req->isUncacheable() && pkt->isWrite()) ||
576 pkt->isResponse());
577
578 return latency;
579 }
580
581 // only misses left
582
583 PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
584
585 bool is_forward = (bus_pkt == nullptr);
586
587 if (is_forward) {
588 // just forwarding the same request to the next level
589 // no local cache operation involved
590 bus_pkt = pkt;
591 }

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610 // to do anything. Otherwise, use the separate bus_pkt to
611 // generate response to pkt and then delete it.
612 if (!is_forward) {
613 if (pkt->needsResponse()) {
614 assert(bus_pkt->isResponse());
615 if (bus_pkt->isError()) {
616 pkt->makeAtomicResponse();
617 pkt->copyError(bus_pkt);
618 } else if (pkt->cmd == MemCmd::WriteLineReq) {
619 // note the use of pkt, not bus_pkt here.
620
621 // write-line request to the cache that promoted
622 // the write to a whole line
623 blk = handleFill(pkt, blk, writebacks,
624 allocOnFill(pkt->cmd));
625 assert(blk != NULL);
626 is_invalidate = false;
627 satisfyRequest(pkt, blk);
628 } else if (bus_pkt->isRead() ||
629 bus_pkt->cmd == MemCmd::UpgradeResp) {
630 // we're updating cache state to allow us to
631 // satisfy the upstream request from the cache

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671{
672 MSHR::Target *initial_tgt = mshr->getTarget();
673 // First offset for critical word first calculations
674 const int initial_offset = initial_tgt->pkt->getOffset(blkSize);
675
676 const bool is_error = pkt->isError();
677 // allow invalidation responses originating from write-line
678 // requests to be discarded
679 bool is_invalidate = pkt->isInvalidate();
680
681 MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
682 for (auto &target: targets) {
683 Packet *tgt_pkt = target.pkt;
684 switch (target.source) {
685 case MSHR::Target::FromCPU:
686 Tick completion_time;
687 // Here we charge on completion_time the delay of the xbar if the

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701 // unlike the other packet flows, where data is found in other
702 // caches or memory and brought back, write-line requests always
703 // have the data right away, so the above check for "is fill?"
704 // cannot actually be determined until examining the stored MSHR
705 // state. We "catch up" with that logic here, which is duplicated
706 // from above.
707 if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
708 assert(!is_error);
709 // we got the block in a writable state, so promote
710 // any deferred targets if possible
711 mshr->promoteWritable();
712 // NB: we use the original packet here and not the response!
713 blk = handleFill(tgt_pkt, blk, writebacks,
714 targets.allocOnFill);
715 assert(blk);
716
717 // discard the invalidation response
718 is_invalidate = false;
719 }
720
721 if (blk && blk->isValid() && !mshr->isForward) {
722 satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade());
723
724 // How many bytes past the first request is this one
725 int transfer_offset =
726 tgt_pkt->getOffset(blkSize) - initial_offset;

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