1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1062
1063 pkt->allocate();
1064 DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(),
1065 cpu_pkt->print());
1066 return pkt;
1067}
1068
1069
1070Tick
1071Cache::recvAtomic(PacketPtr pkt)
1072{
1073 // We are in atomic mode so we pay just for lookupLatency here.
1074 Cycles lat = lookupLatency;
1075
1076 // Forward the request if the system is in cache bypass mode.
1077 if (system->bypassCaches())

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1113 PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
1114 writebacks.push_back(wb_pkt);
1115 pkt->setSatisfied();
1116 }
1117
1118 // handle writebacks resulting from the access here to ensure they
1119 // logically proceed anything happening below
1120 doWritebacksAtomic(writebacks);
1121
1122 if (!satisfied) {
1123 // MISS
1124
1125 // deal with the packets that go through the write path of
1126 // the cache, i.e. any evictions and writes
1127 if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean ||
1128 (pkt->req->isUncacheable() && pkt->isWrite())) {
1129 lat += ticksToCycles(memSidePort->sendAtomic(pkt));
1130 return lat * clockPeriod();
1131 }
1132 // only misses left
1133
1134 PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
1135
1136 bool is_forward = (bus_pkt == nullptr);
1137
1138 if (is_forward) {
1139 // just forwarding the same request to the next level
1140 // no local cache operation involved
1141 bus_pkt = pkt;
1142 }
1143
1144 DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__,
1145 bus_pkt->print());
1146
1147#if TRACING_ON
1148 CacheBlk::State old_state = blk ? blk->status : 0;
1149#endif
1150
1151 lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
1152
1153 bool is_invalidate = bus_pkt->isInvalidate();
1154
1155 // We are now dealing with the response handling
1156 DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__,
1157 bus_pkt->print(), old_state);
1158
1159 // If packet was a forward, the response (if any) is already
1160 // in place in the bus_pkt == pkt structure, so we don't need
1161 // to do anything. Otherwise, use the separate bus_pkt to
1162 // generate response to pkt and then delete it.
1163 if (!is_forward) {
1164 if (pkt->needsResponse()) {
1165 assert(bus_pkt->isResponse());
1166 if (bus_pkt->isError()) {
1167 pkt->makeAtomicResponse();
1168 pkt->copyError(bus_pkt);
1169 } else if (pkt->cmd == MemCmd::WriteLineReq) {
1170 // note the use of pkt, not bus_pkt here.
1171
1172 // write-line request to the cache that promoted
1173 // the write to a whole line
1174 blk = handleFill(pkt, blk, writebacks,
1175 allocOnFill(pkt->cmd));
1176 assert(blk != NULL);
1177 is_invalidate = false;
1178 satisfyRequest(pkt, blk);
1179 } else if (bus_pkt->isRead() ||
1180 bus_pkt->cmd == MemCmd::UpgradeResp) {
1181 // we're updating cache state to allow us to
1182 // satisfy the upstream request from the cache
1183 blk = handleFill(bus_pkt, blk, writebacks,
1184 allocOnFill(pkt->cmd));
1185 satisfyRequest(pkt, blk);
1186 maintainClusivity(pkt->fromCache(), blk);
1187 } else {
1188 // we're satisfying the upstream request without
1189 // modifying cache state, e.g., a write-through
1190 pkt->makeAtomicResponse();
1191 }
1192 }
1193 delete bus_pkt;
1194 }
1195
1196 if (is_invalidate && blk && blk->isValid()) {
1197 invalidateBlock(blk);
1198 }
1199 }
1200
1201 // Note that we don't invoke the prefetcher at all in atomic mode.
1202 // It's not clear how to do it properly, particularly for
1203 // prefetchers that aggressively generate prefetch candidates and
1204 // rely on bandwidth contention to throttle them; these will tend
1205 // to pollute the cache in atomic mode since there is no bandwidth
1206 // contention. If we ever do want to enable prefetching in atomic

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