1/*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1811 }
1812
1813 return true;
1814}
1815
1816CacheBlk*
1817Cache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
1818{
1819 CacheBlk *blk = tags->findVictim(addr);
1820
1821 // It is valid to return nullptr if there is no victim
1822 if (!blk)
1823 return nullptr;
1824
1825 if (blk->isValid()) {
1826 Addr repl_addr = tags->regenerateBlkAddr(blk);

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2797 : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
2798{
2799}
2800
2801Cache*
2802CacheParams::create()
2803{
2804 assert(tags);
2805
2806 return new Cache(this);
2807}
2808///////////////
2809//
2810// MemSidePort
2811//
2812///////////////

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