1/*
2 * Copyright (c) 2010-2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1016 cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
1017 // Even though this SC will fail, we still need to send out the
1018 // request and get the data to supply it to other snoopers in the case
1019 // where the determination the StoreCond fails is delayed due to
1020 // all caches not being on the same local bus.
1021 cmd = MemCmd::SCUpgradeFailReq;
1022 } else {
1023 // block is invalid
1024 cmd = needsWritable ? MemCmd::ReadExReq :
1025 (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
1026 }
1027 PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
1028
1029 // if there are upstream caches that have already marked the
1030 // packet as having sharers (not passing writable), pass that info
1031 // downstream
1032 if (cpu_pkt->hasSharers() && !needsWritable) {
1033 // note that cpu_pkt may have spent a considerable time in the

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