1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53
54#include "mem/cache/cache.hh"
55
56#include "base/misc.hh"
57#include "base/types.hh"
58#include "debug/Cache.hh"
59#include "debug/CachePort.hh"
60#include "debug/CacheTags.hh"
61#include "mem/cache/blk.hh"
62#include "mem/cache/mshr.hh"
63#include "mem/cache/prefetch/base.hh"
64#include "sim/sim_exit.hh"
65
66Cache::Cache(const CacheParams *p)
67 : BaseCache(p, p->system->cacheLineSize()),
68 tags(p->tags),

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174 if (blk->checkWrite(pkt)) {
175 pkt->writeDataToBlock(blk->data, blkSize);
176 }
177 // Always mark the line as dirty (and thus transition to the
178 // Modified state) even if we are a failed StoreCond so we
179 // supply data to any snoops that have appended themselves to
180 // this cache before knowing the store will fail.
181 blk->status |= BlkDirty;
182 DPRINTF(Cache, "%s for %s addr %#llx size %d (write)\n", __func__,
183 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
184 } else if (pkt->isRead()) {
185 if (pkt->isLLSC()) {
186 blk->trackLoadLocked(pkt);
187 }
188
189 // all read responses have a data payload
190 assert(pkt->hasRespData());
191 pkt->setDataFromBlock(blk->data, blkSize);

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275 }
276 } else {
277 // Upgrade or Invalidate
278 assert(pkt->isUpgrade() || pkt->isInvalidate());
279
280 // for invalidations we could be looking at the temp block
281 // (for upgrades we always allocate)
282 invalidateBlock(blk);
283 DPRINTF(Cache, "%s for %s addr %#llx size %d (invalidation)\n",
284 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
285 }
286}
287
288
289/////////////////////////////////////////////////////
290//
291// MSHR helper functions

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311{
312 // sanity check
313 assert(pkt->isRequest());
314
315 chatty_assert(!(isReadOnly && pkt->isWrite()),
316 "Should never see a write in a read-only cache %s\n",
317 name());
318
319 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
320 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
321
322 if (pkt->req->isUncacheable()) {
323 DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(),
324 pkt->req->isInstFetch() ? " (ifetch)" : "",
325 pkt->getAddr());
326
327 // flush and invalidate any existing block

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1217 (mshr && mshr->inService && mshr->isPendingModified()));
1218
1219 bool done = have_dirty
1220 || cpuSidePort->checkFunctional(pkt)
1221 || mshrQueue.checkFunctional(pkt, blk_addr)
1222 || writeBuffer.checkFunctional(pkt, blk_addr)
1223 || memSidePort->checkFunctional(pkt);
1224
1225 DPRINTF(Cache, "functional %s %#llx (%s) %s%s%s\n",
1226 pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns",
1227 (blk && blk->isValid()) ? "valid " : "",
1228 have_data ? "data " : "", done ? "done " : "");
1229
1230 // We're leaving the cache, so pop cache->name() label
1231 pkt->popLabel();
1232
1233 if (done) {

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1528 if (isCachedAbove(wcPkt))
1529 delete wcPkt;
1530 else
1531 allocateWriteBuffer(wcPkt, forward_time);
1532 }
1533 blk->invalidate();
1534 }
1535
1536 DPRINTF(Cache, "Leaving %s with %s for addr %#llx\n", __func__,
1537 pkt->cmdString(), pkt->getAddr());
1538 delete pkt;
1539}
1540
1541PacketPtr
1542Cache::writebackBlk(CacheBlk *blk)
1543{
1544 chatty_assert(!isReadOnly || writebackClean,

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1876 pkt->cmd = MemCmd::ReadRespWithInvalidate;
1877 }
1878 // Here we consider forward_time, paying for just forward latency and
1879 // also charging the delay provided by the xbar.
1880 // forward_time is used as send_time in next allocateWriteBuffer().
1881 Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
1882 // Here we reset the timing of the packet.
1883 pkt->headerDelay = pkt->payloadDelay = 0;
1884 DPRINTF(Cache, "%s created response: %s addr %#llx size %d tick: %lu\n",
1885 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(),
1886 forward_time);
1887 memSidePort->schedTimingSnoopResp(pkt, forward_time, true);
1888}
1889
1890uint32_t
1891Cache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
1892 bool is_deferred, bool pending_inval)
1893{
1894 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
1895 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1896 // deferred snoops can only happen in timing mode
1897 assert(!(is_deferred && !is_timing));
1898 // pending_inval only makes sense on deferred snoops
1899 assert(!(pending_inval && !is_deferred));
1900 assert(pkt->isRequest());
1901
1902 // the packet may get modified if we or a forwarded snooper

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1958 // cache-to-cache response from some upper cache:
1959 // forward response to original requester
1960 assert(pkt->isResponse());
1961 }
1962 }
1963 }
1964
1965 if (!blk || !blk->isValid()) {
1966 DPRINTF(Cache, "%s snoop miss for %s addr %#llx size %d\n",
1967 __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1968 return snoop_delay;
1969 } else {
1970 DPRINTF(Cache, "%s snoop hit for %s for addr %#llx size %d, "
1971 "old state is %s\n", __func__, pkt->cmdString(),
1972 pkt->getAddr(), pkt->getSize(), blk->print());
1973 }
1974
1975 chatty_assert(!(isReadOnly && blk->isDirty()),
1976 "Should never have a dirty block in a read-only cache %s\n",
1977 name());
1978
1979 // We may end up modifying both the block state and the packet (if
1980 // we respond in atomic mode), so just figure out what to do now

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2068
2069 return snoop_delay;
2070}
2071
2072
2073void
2074Cache::recvTimingSnoopReq(PacketPtr pkt)
2075{
2076 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
2077 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
2078
2079 // Snoops shouldn't happen when bypassing caches
2080 assert(!system->bypassCaches());
2081
2082 // no need to snoop requests that are not in range
2083 if (!inRange(pkt->getAddr())) {
2084 return;

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